Continuous Mode (Slave Mode, Reception Mode) - NEC V850E/RS1 User Manual

13.7.7 Continuous mode (slave mode, reception mode)

Figure 13-15 shows the transfer timing when data is transferred with the MSB first (CBnDIR bit of
CBnCTL0 register = 0), when continuous transfer mode (CBnTMS bit of CBnCTL0 register = 1), when
the CBnCKP bit of the CBnCTL1 register = 0, when the CBnDAP bit of the CBnCTL1 register = 0, and
when the transfer data length is 8 bits (CBnCL3 to CBnCL0 bits of the CBnCTL2 register = 0, 0, 0, 0).
(1) Clear the CBnPWR bit of the CBnCTL0 register.
(2) Specify the transfer mode by setting the CBnCTL1 and CBnCTL2 registers.
(3) Specify the transfer mode by using the CBnDIR bit of the CBnCTL0 register and, at the same time,
enable reception by setting the CBnRXE and CBnCSE bits of the CBnCTL0 register to 1.
(4) Enable CSIB operating clock supply by setting the CBnPWR bit of the CBnCTL0 register to 1.
(5) Read dummy data from the CBnRX register (reception start trigger).
(6) The reception complete interrupt request signal (INTCBnR) is generated to inform the CPU that
the CBnRX register can be read. Read the CBnRX register before the next receive data arrives or
before the CBnPWR bit is cleared to 0.
(7) Confirm that the CBnTSF bit of the CBnSTR register = 0, and stop clock supply to CSIB by clear-
ing the CBnPWR bit to 0 (end of reception).
To transfer more data, repeat (5) and (6) before (7).
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Chapter 13 3-Wire Serial Interface (CSIB)
Figure 13-15: Continuous Transfer Timing (Slave Mode, Reception Mode)
SCKBn
SIBn 0 1
INTCBnR
CBnTSF
Shift
register
CBnRX
(1) - (4) (5)
User's Manual U16702EE3V2UD00
0 1 0 1 0 1 1 0
55H
55H
(6)
1 0 1 0 1 0
AAH 00H
AAH 00H
(6) (7)
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