NEC V850E/RS1 User Manual page 19

Figure 4-81:
Figure 4-82:
Figure 4-83:
Figure 4-84:
Figure 4-85:
Figure 4-86:
Figure 4-87:
Figure 4-88:
Figure 4-89:
Figure 4-90:
Figure 4-91:
Figure 4-92:
Figure 4-93:
Figure 4-94:
Figure 4-95:
Figure 4-96:
Figure 4-97:
Figure 4-98:
Figure 4-99:
Figure 4-100:
Figure 4-101:
Figure 5-1:
Figure 5-2:
Figure 5-3:
Figure 5-4:
Figure 5-5:
Figure 5-6:
Figure 5-7:
Figure 5-8:
Figure 5-9:
Figure 5-10:
Figure 5-11:
Figure 5-12:
Figure 5-13:
Figure 5-14:
Figure 6-1:
Figure 6-2:
Figure 6-3:
Figure 6-4:
Figure 6-5:
Figure 6-6:
Figure 6-7:
Figure 6-8:
Figure 6-9:
Figure 6-10:
Figure 6-11:
Figure 6-12:
Figure 6-13:
Figure 6-14:
Figure 6-15:
Figure 6-16:
Figure 6-17:
Figure 7-1:
Figure 7-2:
Figure 7-3:
Figure 7-4:
Figure 7-5:
Figure 7-6:
Downloaded from Elcodis.com electronic components distributor
Type W-SDW11 Block Diagram ................................................................................ 185
Type E-SD7 Block Diagram ...................................................................................... 186
Type A-1 Block Diagram ........................................................................................... 187
Type U-SDW11E Block Diagram............................................................................... 188
Type G-SD7A Block Diagram.................................................................................... 189
Type G-SDW8E Block Diagram ................................................................................ 190
Type G-SD6 Block Diagram ...................................................................................... 191
Type G-SDJ2 Block Diagram .................................................................................... 192
Type G-SDJ5 Block Diagram .................................................................................... 193
Type G-SDJ8E Block Diagram .................................................................................. 194
Type E-DWJ4 Block Diagram.................................................................................... 195
Type U-SDW11 Block Diagram ................................................................................. 196
Type W-SD11 Block Diagram ................................................................................... 197
Type W-SD12E Block Diagram ................................................................................. 198
Type U-SDW10 Block Diagram ................................................................................. 199
Type G-SDW6 Block Diagram................................................................................... 200
Type E-D1 Block Diagram ......................................................................................... 201
Type E-D4 Block Diagram ......................................................................................... 202
Type D-7E Block Diagram ......................................................................................... 203
Type C-D1 Block Diagram......................................................................................... 204
Type B Block Diagram............................................................................................... 205
Data Memory Map ..................................................................................................... 209
Bus Size Configuration Register (BSC) Format ....................................................... 212
Little-Endian Address in Word ................................................................................... 213
Data Wait Control Register 0 (DWC0) Format ......................................................... 219
Example of Inserting Wait States in Separate Bus Mode.......................................... 220
Address Wait Control Register (AWC) Format ......................................................... 221
Bus Cycle Control Register (BCC) Format ............................................................... 222
Bus Hold Status Transition Procedure ...................................................................... 224
Bus Read Timing (Bus Size: 16 bit, 16-bit Access) ................................................... 226
Bus Read Timing (Bus Size: 8 bit) ............................................................................ 227
Bus Write Timing (Bus Size: 16 bit, 16-bit Access) ................................................... 228
Bus Write Timing (Bus Size: 8 bit)............................................................................. 229
Address Wait Timing (Bus Size: 16 bit) ..................................................................... 230
Bus Hold Timing (Bus Size: 16 bit)............................................................................ 231
Clock Generator ........................................................................................................ 234
Main Peripheral Clock Control Register (MPCCTL) Format (1/2) ............................ 235
Extension Clock Select Register (EXCKSEL) Format .............................................. 237
Power Save Mode Register (PSMR) Format ............................................................ 238
Processor Clock Control Register (PCC) Format ..................................................... 239
CPU Operation Clock Status Register (CCLS) Format ............................................ 240
Ring-OSC Mode Register (RCM) Format ................................................................. 240
Oscillation Stabilization Time Select Register (OSTS) Format ................................. 241
Clock Selection Register 2 (OCKS2) Format ........................................................... 242
PLL Control Register (PLLCTL0) Format ................................................................. 245
PLL Control Register (PLLCTL1) Format ................................................................. 245
PLL Lockup Time Specification Register (PLLS) ...................................................... 246
Clock Control Register (CKC) Format ...................................................................... 247
Clock Selection Register 0 (OCKS0) Format ........................................................... 248
Clock Selection Register 1 (OCKS1) Format ........................................................... 249
Programmable Clock Mode Register (PCLM) Format .............................................. 250
Clock Selection Register 3 (OCKS3) Format ........................................................... 251
Block Diagram of Timer P ......................................................................................... 257
Capture/Compare Register 0 (TPnCCR0) Format ................................................... 258
Capture/Compare Register 1 (TPnCCR1) Format ................................................... 259
TMPn Timer Read Buffer Register (TPnCNT) Format ............................................. 260
TMPn Control Register 0 (TPnCTL0) Format ........................................................... 261
TMPn Control Register 1 (TPnCTL1) Format (1/2) .................................................. 262
User's Manual U16702EE3V2UD00 19