NEC V850E/RS1 User Manual page 510

DA25 - DA0
The number of relevant bits of DA25 - DA0 is as follows:
Internal RAM
External Memory
On-chip Peripheral I/O
Caution:
(5) DMA transfer count register (DMBCn)
The DMBCn register sets the transfer count for DMA channel n. It holds the number of remaining
transfers during a DMA transfer. The value is decremented with each transfer and hold a value of
0 at the end of a DMA transfer. The register can be read or written in 16-bit units.
Caution:
DMBCn BC15 BC14 BC13 BC12 BC11 BC10 BC9 BC8 BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0
R/W
BC15 - BC0
Note: When the value of DMBCn register is read as 0, it can either mean that there is one remaining
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Chapter 15 DMA Functions (DMA Controller)
Figure 15-6: DMA Destination Address Register (DMDAn) Format (2/2)
DMA transfer destination address (address signals A25 - A0).
If address increment is selected for the DMA transfer, the address will be updated after
each transfer to the next transfer address.
Transfer object
Set the lower 16-bit address for DA15 - DA0
Set the lower 26-bit address for DA25 - DA0
Set the lower 14-bit address for DA13 - DA0
SA0 and DA0 have to be set to 0, when DMA transfer size is halfword.
SA0 and DA0 and SA1 and DA1 have to be set to 0, when DMA transfer size is word.
Write to DMBCn is permitted only when EN = 0 (DMCHCn register).
Figure 15-7: DMA Transfer Count Register (DMBCn) Format
DMBC0=FFFFFE10H, DMBC1=FFFFFE1CH, DMBC2=FFFFFE28H,
DMBC3=FFFFFE34H, DMBC4=FFFFFE40H, DMBC5=FFFFFE4CH
15 14 13 12 11 10
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
0000H
1 transfer remaining
0001H 2 transfers remaining
... ...
FFFFH 65536 transfers remaining
transfer pending, or that the transfer is completed. The EN bit can be used to determine if a fur-
ther transfer is pending or if the transfer is completed.
Setting of DA25 - DA0
9 8 7 6 5 4
DMA Transfer Counter
Note
User's Manual U16702EE3V2UD00
3 2 1 0 Address
After
reset
undef.