NEC V850E/RS1 User Manual page 347

capture interrupt
capture interrupt
match interrupt
match interrupt
Remarks: 1. D00, D01, D02, D03: Values captured to TQnCCR0 register (0000H to FFFFH)
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Chapter 8 16-Bit Timer/Event Counter Q
Figure 8-29: Basic Operation Timing in Free-Running Mode (3/4)
(c) (TQnCCS3 = 1, TQnCCS2 = 1, TQnCCS1 = 1, TQnCCS0 = 0)
TQnCE = 1
FFFFH
16-bit
counter
D
30
TIQn0
INTTQnCC0 0000H
INTTQnCC0
TIQn1
TQnCCR1 0000H
INTTQnCC1
TQnCCR2
CCR2 buffer
0000H
register
INTTQnCC2
TQnCCR3
CCR3 buffer
0000H
register
INTTQnCC3
D10, D11, D12, D13: Values captured to TQnCCR1 register (0000H to FFFFH)
D20, D21: Setting values of TQnCCR2 register (0000H to FFFFH)
D30: Setting value of TQnCCR3 register (0000H to FFFFH)
2. TIQn0: Set to rising edge detection (TQnIS1, TQnIS0 = 01)
TIQn1: Set to falling edge detection (TQnIS3, TQnIS2 = 10)
3. n = 0 to 1
User's Manual U16702EE3V2UD00
D
10
D D
20
D
00
D
11
D
01
D
30
D D
00
D
10
D
20
D
20
D
30
D
D
12
D
02
D
20
D
03
D
21
D
30
D
01 02
D D
11 12
D
21
D
21
30
13
D
03
D
13
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