NEC V850E/RS1 User Manual page 236

STPPLL0
0
1
Cautions: 1. If this bit is set to "1", it is impossible to set to "0" by register writing. Only
236
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Chapter 6 Clock Generator
Figure 6-2: Main Peripheral Clock Control Register (MPCCTL) Format (2/2)
PLL0 executable (Default)
PLL0 stop
RESET input can be set to "0".
2. When using PLL0 clock for peripheral functions, do not set to 1 this bit.
User's Manual U16702EE3V2UD00
PLL 0 execution stop register