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Timer Q dedicated I/O control register 2 (TQnIOC2)
The TQnIOC2 register is an 8-bit register that controls the valid edge of the external event count
input signal (TIQn0) and external trigger input signal (TIQn0).
This register can be read or written in 8-bit or 1-bit units.
RESET input clears this register to 00H.
Symbol
TQ0IOC2
Symbol
TQ1IOC2
TQnEES1
TQnETS1
Cautions: 1. Rewrite bits TQnEES1, TQnEES0, TQnEST1, and TQnEST0 when TQnCE = 0. (The
Remark:
316
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Chapter 8 16-Bit Timer/Event Counter Q
Figure 8-11: Timer Q Dedicated I/O Control Register 2 (TQnIOC2) Format
7
6
5
4
0
0
0
0
7
6
5
4
0
0
0
0
TQnEES0
0
0
Detect no edge (external event count is invalid).
0
1
Detection of rising edge
1
0
Detection of falling edge
1
1
Detection of both edges
TQnETS0
0
0
Detect no edge (external trigger is invalid).
0
1
Detection of rising edge
1
0
Detection of falling edge
1
1
Detection of both edges
same value can be written when TQnCE = 1.) If rewriting was mistakenly
performed, set TQnCE = 0 and then set the bits again.
2. The TQnEES1 and TQnEES0 bits are valid when TQnEEE = 1 or when the external
event count mode is set (TQnMD2 to TQnMD0 of TIQnCTL1 register = 001).
n = 0, 1
User's Manual U16702EE3V2UD00
3
2
1
TQ0EES1 TQ0EES0 TQ0ETS1 TQ0ETS0 FFFFF544H R/W 00H
3
2
1
TQ1EES1 TQ1EES0 TQ1ETS1 TQ1ETS0 FFFFF614H R/W 00H
Setting of valid edge of external event count input (TIQn0)
Setting of valid edge of external trigger input (TIQn0)
After
0
Address
R/W
reset
After
0
Address
R/W
reset
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