NEC V850E/RS1 User Manual page 238

(3) Power save mode register (PSMR)
This is an 8-bit register that controls the operation status in the power save mode and the clock
operation.
This register can be read or written in 8-bit or 1-bit units. Be sure to clear bits 2 to 7 of the PSMR
register to 0.
Symbol
PSMR
R/W
PSM1
0
0
1
1
Caution:
Remark:
Note: Refer to Chapter 18 "Standby Function" on page 723 to get information about standby
238
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Figure 6-4: Power Save Mode Register (PSMR) Format
7 6 5
0 0 0
R/W R R/W
PSM0
0 IDLE1 mode
1 STOP mode
0 IDLE2 mode
1 Setting prohibited
The PSM0 and PSM1 bits are valid only when the STP bit of the PSC register is 1.
IDLE1: In this mode, all operations except the oscillator operation, flash memory, and PLL
are stopped. After the IDLE1 mode is released, the normal mode do not need to
wait the lapse of the oscillation stabilization time.
IDLE2: In this mode, all operations except the oscillator and flash memory operation are
stopped. After the IDLE2 mode is released, the normal mode is returned to
following the lapse of the setup time (flash memory, PLL) specified by the OSTS
register.
STOP: In this mode, all operations are stopped, except the ring oscillator operation.
After the STOP mode is released, the normal mode is returned to following the
lapse of the oscillation stabilization time specified by the OSTS register.
mode release.
Chapter 6 Clock Generator
4 3 2
0 0 0 PSM1
R/W R R R/W
Software standby mode select
User's Manual U16702EE3V2UD00
1 0 Address After reset
PSM0 FFFFF820H
R/W
00H