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The V850E/RS1 includes two 3-wire serial interfaces (CSIB).
13.1 Features
•
Master mode and slave mode selectable
•
3-wire serial interface for 8-bit to 16-bit transfer
•
Interrupt request signals (INTCBnT and INTCBnR)
•
Serial clock and data phase selectable
•
Transfer data length selectable from 8 to 16 bits in 1-bit units
•
Data transfer with MSB- or LSB-first selectable
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3-wire
•
Transmission mode, reception mode, and transmission/reception mode selectable
Remark:
13.2 Configuration
CSIB consists of the following hardware:
Remark:
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Chapter 13 3-Wire Serial Interface (CSIB)
SOBn:
SIBn:
SCKBn:
n = 0, 1
Table 13-1: Configuration of CSIB0, CSIB1
Item
CSIBn reception data register (CBnRX)
Register
CSIBn transmit data register (CBnTX)
Reception data input
2 (SIB0, SIB1)
Transmit data output
2 (SOB0, SOB1)
Serial clock input/output
2 (SCKB0, SCKB1)
CSIBn control register 0 to 2 (CBnCTL0 to CBnCTL2)
Control register
CSIBn status register (CBnSTR)
n = 0, 1
User's Manual U16702EE3V2UD00
Serial data output
Serial data input
Serial clock I/O
Configuration
431
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