NEC V850E/RS1 User Manual page 365

(2) Operation as Watchdog timer 2
Watchdog timer 2 automatically starts in the reset mode following reset release.
The WDTM2 register can be written to only once following reset using byte access. To use
Watchdog timer 2, write the operation mode and the interval time to the WDTM2 register using an
8-bit memory manipulation instruction. After this, the operation of Watchdog timer 2 cannot be
stopped.
The WDCS24 to WDCS20 bits of the WDTM2 register are used to select the Watchdog timer 2
loop detection time interval. Writing ACH to the WDTE register clears the counter of Watchdog
timer 2 and starts the count operation again. After the count operation has started, write ACH to
WDTE within the loop detection time interval.
If the time interval expires without ACH being written to the WDTE register, a reset signal
(WDT2RES) or a non-maskable interrupt request signal (INTWDT2) is generated, depending on
the set values of the WDM21 and WDM20 bits of the WDTM2 register.
To not use Watchdog timer 2, write 1FH to the WDTM2 register.
If the non-maskable interrupt request mode has been set, restoring using the RETI instruction
following non-maskable interrupt servicing is not possible. Therefore, following completion of
interrupt servicing, perform a system reset.
Caution:
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Chapter 10 Functions of Watchdog Timer 2
If the set to WDTM2, WDM21 bit = 1 (reset mode), WDT overflow occurred in
oscillation stabilization time, after reset or standby release, internal reset is not
occurred, CPU clock changing for RING-OSC.
User's Manual U16702EE3V2UD00 365