NEC V850E/RS1 User Manual page 498

(8) FIFO Buffer Transfer Mode (Master Mode, Receive Only Mode)
MSB first (DIR = 0), no INTC3nI delay (CSIT = 0), transmission wait disabled (CSWE = 0), CS
inactive disabled (CSMD = 0), CKP = 0, DAP = 1, transmission data length of 8 bits
(CCL[3:0] = [1,0,0,0]), active levels of all chip selects set to "active low":
SFDB write
UF-empty
CSIB CSIBUF_0
CSIBUF_1
CSIBUF_2
CS3n[3:0]
SIRB read
1. Set the CSIM register's POWER bit to 1 to enable the supply of the Queued CSI operation clock.
2. Set the CSIC and CSIL registers to specify the transfer mode.
3. Write "1" in the SFA register's FPCLR bit to clear all FIFO pointers.
4. Specify the transfer mode using the CSIM register's TRMD, DIR, and CSIT bits; at the same time,
set the CRXE bit to 1 to enable the receive operation.
5. Set the number of receive-data items in the SFN register's SFN[3:0] bits.
6. Make sure that the SFA register's SFFUL bit is set to 0, then write chip-select data and dummy
transmission data in the SFCS and SFDB registers in this order (start-of-receive trigger).
7. Wait for the receptions to be completed (e.g. by monitoring the INT3C3nI interrupt).
8. Read the received data by multiple read of the SIRB register (= sequential read from the FIFO).
9. Write "1" in the SFA register's FPCLR bit and clear all FIFO pointers for the next transmission.
To continue reception, repeat steps (5) - (9).
10. Set the CSIM register's CRXE bit to 0 to disable the receive operation (end of receive operation).
Remark:
498
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Chapter 14 Queued CSI (CSI30, CSI31)
Figure 14-32: FIFO Buffer Transfer Mode (Master, Receive Only) Timing
CRXE
dummy
dumm y
SCK3
SI3
0 1 0 1 0
"active-L" CS 0
CSO T
INTC3nI
SFN3-0 3H
SFP3-0 0H
(1) (2)(3) (5)
(6)
(4)
(6)
The SO3n pin is invalid and maintains its signal level, as the output latch is disabled.
55H
AAH
1 0 1 0 1 0 1 0 1 0
1
CS 1
1H
2H
Wait insertion
by CSIBUF-empty
User's Manual U16702EE3V2UD00
CCH
dummy
1 1 0 0 1 1 0 0
CS 2
3H
(7)
(9)
(6) (8)
(8)
(8)
0H
(10)