NEC V850E/RS1 User Manual page 251

(2) Clock selection register 3 (OCKS3)
This is an 8-bit register that controls the operation enable and clock selection for PCL output.
Symbol
OCKS3
R/W
OCKSEN3
OCKSTH3
Remark:
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Figure 6-17: Clock Selection Register 3 (OCKS3) Format
7 6 5
0 0 0 OCKSEN3 OCKSTH3
R R R
0 Operation Disable
1 Operation Enable
0 Output clock is divided clock by setting OCKS31 and OCKS30
Output clock is through (f
1
OCKS31 OCKS30
0 0
0 1
1 0
1 1
OCKSEN3 bit disables only the divider factor function. If OCKSEN3 bit is set to 0 and
OCKSTH3 bit is set to 1, the PCL outputs f
User's Manual U16702EE3V2UD00
Chapter 6 Clock Generator
4 3 2
0 OCKS31 OCKS30 FFFFF86CH
R/W R/W R
Specified for execution enable
Specified for output clock through or divide
)
PCL1
Specified for divider factor
f = f
PCL
f = f
PCL
f = f
PCL
f = f
PCL
frequency.
PCL1
1 0 Address
R/W R/W
/2
PCL1
/3
PCL1
/4
PCL1
/5
PCL1
After reset
00H
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