NEC V850E/RS1 User Manual page 293

(1) When TPnCCS1 = 0, and TPnCCS0 = 0 settings (interval function description, compare
function)
When TPnCE = 1 is set, the 16-bit counter counts from 0000H to FFFFH and the free-running
count-up operation continues until TPnCE = 0 is set. In this mode, when a value is written to the
TPnCCR0 and TPnCCR1 registers, they are transferred to the CCR0 buffer register and the CCR1
buffer register (any time write mode). In this mode, no one-shot pulse is output even when an
one-shot pulse trigger is input. Moreover, when TPnOEm = 1 is set, TOPnm performs toggle
output upon a match between the 16-bit counter and the CCRm buffer register.
Figure 7-28: Basic Operation Timing in Free-Running Mode (TPnCCS1 = 0, TPnCCS0 = 0)
CCR0 buffer
INTTPnCC0
match interrupt
CCR1 buffer
INTTPnCC1
match interrupt
Remarks: 1. D00, D01: Setting values of TPnCCR0 register (0000H to FFFFH)
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Chapter 7 16-Bit Timer/Event Counter P
(TPnOE0 = 1, TPnOE1 = 1, TPnOL0 = 0, TPnOL1 = 0)
TPnCE = 1
FFFFH
16-bit
D
00
counter
D
10
TPnCCR0
0000H
register
TPnCCR1
register 0000H
TOPn0
TOPn1
INTTPnOV
TPnOVF
D10, D11: Setting values of TPnCCR1 register (0000H to FFFFH)
2. Toggle width of TOPn0 output = (Set value of TPnCCR0 register) x (Count clock cycle)
Toggle width of TOPn1 output = (Set value of TPnCCR1 register) x (Count clock cycle)
3. TOPnm output goes high when counting is started.
4. n = 0 to 3
m = 0, 1
User's Manual U16702EE3V2UD00
D
11
D
00
D
00
D
00
D
10
D
10
Clear by writing 0 to TPnOVF
D
01
D
11
D
01
D
01
D
11
D
11
Clear by writing 0 to TPnOVF
293