NEC V850E/RS1 User Manual page 345

match interrupt
match interrupt
match interrupt
match interrupt
Remarks: 1. D00, D01: Setting values of TQnCCR0 register (0000H to FFFFH)
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Chapter 8 16-Bit Timer/Event Counter Q
Figure 8-29: Basic Operation Timing in Free-Running Mode (1/4)
(a) (TQnCCS3 = 0, TQnCCS2 = 0, TQnCCS1 = 0, TQnCCS0 = 0)
TQnCE = 1
FFFFH
D
16-bit
D
10
counter
TQnCCR0
CCR0 buffer
0000H
register
INTTQnCC0
TOQn0
TQnCCR1 D
10
CCR1 buffer
0000H D
register
INTTQnCC1
TOQn1
TQnCCR2
CCR2 buffer
0000H
register
INTTQnCC2
TOQn2
TQnCCR3
CCR3 buffer
0000H
register
INTTQnCC3
TOQn3
D10, D11: Setting values of TQnCCR1 register (0000H to FFFFH)
D20: Setting value of TQnCCR2 register (0000H to FFFFH)
D30, D31: Setting values of TQnCCR3 register (0000H to FFFFH)
2. Toggle width of TOQnm output = (Set value of TQnCCRm register) × (Count clock cycle)
3. TOQnm output goes high when counting is started.
4. n = 0 to 1, m = 0 to 3
User's Manual U16702EE3V2UD00
D
30
D
20
D
D
00 00
D
00
D
00
10
D
20
D
D
30
D
30
D
30
D
D
20
20
D
11
11
D
31
D
01
D
01
D
11
D
11
20
D
31
D
31
D
01
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