Configuration - NEC V850E/RS1 User Manual

6.2 Configuration

PSMR (STOP)
PCC.MFR
X1
X2
MPCCTL.STPPLL0
MPCCTL.STPPLL1
MPCCTL.MCKSEL
MPCCTL.PCKSEL
(1) Main clock oscillator (Main OSC)
The main resonator oscillates the following frequencies (f
• In clock-through mode
• In PLL mode
(2) PLL
This circuit multiplies the clock generated by the main clock oscillator (f
It operates in two modes: clock-through mode in which f
multiplied clock is output. These modes can be selected by using the SELPLL bit of the Main
peripheral clock control register (MPCCTL). Operation of the PLL can be started or stopped by the
STPPLL bit of MPCCTL register.
(3) Ring-OSC
Outputs a frequency (f
(4) Prescaler 1 (PRS1)
This prescaler divides the clock to be supplied to the WDT2 and the on-chip peripheral functions.
(5) Prescaler 2 (PRS2)
This circuit divides main clock f
clock and system clock (f
f
CLK
output from the CLKOUT pin.
f
CPU
234
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MPCCTL.SELPLL
BRGC
t _MCKSEL_CKDIV
PLL
PLL
PLL0 (×12)
t _MCKSEL
Main OSC PLL
f
X PLL1 (×10)
OCSK0
OCSK1
CKC.CKDIV0
CKC.CKDIV1
PSMR (IDLE2)
f = 4 to 8 MHz (internal f
X XX
f = 4 to 8 MHz (internal f
X XX
) of 100 to 400 kHz.
R
).
CLK
is supplied to the interrupt controller INTC, ROM controller, ROM and RAM blocks. It can be
is the clock supplied to CPU.
Chapter 6 Clock Generator
Figure 6-1: Clock Generator
PRS1
PSMR (IDLE1)
f
Standby
XX
PRS2
control
Output
PLL
control
PCLM.PCKm
PCLM.PCLE
OCKS3 PCC.CKm
t _PCKSEL
PLL
aFCAN, CSI3n
Output
Extended clock for CSIBm
control
OCKS2
).
X
= 4 to 8 MHz)
= 4 to 40 MHz (µPD70F3403 and µPD70F3403A)
= 4 to 32 MHz (µPD70F3402))
is output as is, and PLL mode in which a
X
(f , f /2, f /4, f /8, f
XX XX XX XX XX XX
User's Manual U16702EE3V2UD00
Peripherals
WDT2
CCLS.CCLSF
PSMR (HALT)
f /32
XX
f /16
XX
f /8
XX
f
Standby
f /4
XX
control
f /2
XX
f
f
XX
f
R
Ring-OSC 1/8
).
X
/16, f /32) to provide the CPU (f
XX
CPU
CPUCLK
CLK
SystemCLK
WDT2
CPU)