NEC V850E/RS1 User Manual page 515

DMBC0 = 02H (3-times transfer)
DMBC3 = 03H (4-times transfer)
Bus status
(DMA channel 0)
(DMA channel 0)
(DMA channel 3)
(DMA channel 3)
DMBC0 = 02H (3-times transfer)
DMBC3 = 03H (4-times transfer)
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Chapter 15 DMA Functions (DMA Controller)
Figure 15-10: DMA Channel Control Register (DMCHCn) Format (3/4)
(b) ACF bit status in channel-fixed single transfer mode
CPU CPU CPU DMA3
DMARQ0
DMARQ3
EN
Set to 1 by Software
ACF
EN
ACF Set to 1 by Software
(c) ACF bit status in block transfer mode
CPU CPU
Bus status
DMARQ0
DMARQ3
EN
(DMA channel 0)
ACF
Set to 1 by Software
(DMA channel 0)
EN
(DMA channel 3)
Set to 1 by Software
ACF
(DMA channel 3)
In this example, the internal bus is occupied by the DMA during these times.
Due to this behavior, the ACF bit during these times cannot be read by the CPU.
If a NMI interrupt occurs during a block transfer mode, then the ACF bit will be read by CPU as an "1".
User's Manual U16702EE3V2UD00
CPU DMA3 CPU DMA3 CPU DMA3
CPU DMA3 DMA3 DMA3 DMA3 CPU
TC
CPU DMA0 CPU DMA0 CPU
TC
CPU DMA0 DMA0 DMA0 CPU CPU
TC
DMA0 CPU
TC
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