NEC V850E/RS1 User Manual page 296

(4) When TPnCCS1 = 0 and TPnCS0 = 1
When TPnCE is set to 1, the 16-bit counter counts from 0000H to FFFFH and free-running
count-up operation continues until TPnCE = 0 is set. The TPnCCR1 register is used as a compare
register. An interrupt signal is output upon a match between the value of the 16-bit counter and the
setting value of the TPnCCR1 register as an interval function. When TPnOE1 = 1 is set, TOPn1
performs toggle output upon mach between the value of the 16-bit counter and the setting value of
the TPnCCR1 register.
Even if TPnOE0 = 1 to realize the output function, TPnCCR0 register cannot control TOPn0
because it is used as capture register.
Figure 7-31: Basic Operation Timing in Free-Running Mode (TPnCCS1 = 0, TPnCCS0 = 1)
TPnCCR0
INTTPnCC0
match interrupt
TPnCCR1
CCR1 buffer
INTTPnCC1
match interrupt
INTTPnOV
Remarks: 1. D00, D01, D02, D03: Values captured to TPnCCR0 register (0000H to FFFFH)
(5) Overflow flag
When the counter overflows from FFFFH to 0000H in the free-running mode, the overflow flag
(TPnOVF) is set to 1 and an overflow interrupt (INTTPnOV) is output.
The overflow flag is cleared by the CPU when writing 0 to it.
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Chapter 7 16-Bit Timer/Event Counter P
(TPnOE0 = 1, TPnOE1 = 1, TPnOL0 = 0, TPnOL1 = 0)
TPnCE = 1
FFFFH
D
10
16-bit
counter
TIPn0
0000H
D
10
0000H D
register
10
TOPn0
L
TOPn1
D10, D11, D12: Setting compare value of TPnCCR1 register (0000H to FFFFH)
2. TIPn0: Set to falling edge detection (TPnIS1, TPnIS0 = 10)
3. n = 0 to 3
User's Manual U16702EE3V2UD00
D
02
D
00
D
01
D
11
D D
00 01
D
11
D
11
D
03
D
12
D
11
D D
02 03
D
12
D
12