Xilinx AC701 User Manual
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Xilinx AC701 User Manual

For the artix-7 fpga
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AC701 Evaluation Board
for the Artix-7 FPGA
User Guide
UG952 (v1.3) April 7, 2015

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Summary of Contents for Xilinx AC701

  • Page 1 AC701 Evaluation Board for the Artix-7 FPGA User Guide UG952 (v1.3) April 7, 2015...

  • Page 2: Revision History

    (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same.
  • Page 3 Table 1-35. Added Figure A-3 to show board components called out in Table A-3. Updated the Artix-7 FPGA AC701 Declaration of Conformity link in Appendix G, Regulatory and Compliance Information. UG952 (v1.3) April 7, 2015 www.xilinx.com AC701 Evaluation Board...
  • Page 4 AC701 Evaluation Board www.xilinx.com UG952 (v1.3) April 7, 2015...

  • Page 5: Table Of Contents

    AC701 Board Power System ........
  • Page 6 Appendix D: Board Setup Installing the AC701 Board in a PC Chassis ....... . . 101...

  • Page 7: Chapter 1: Ac701 Evaluation Board Features

    Chapter 1 AC701 Evaluation Board Features Overview The AC701 evaluation board for the Artix®-7 FPGA provides a hardware environment for developing and evaluating designs targeting the Artix-7 XC7A200T-2FBG676C FPGA. The AC701 board provides features common to many embedded processing systems, including a DDR3 SODIMM memory, an 4-lane PCI Express®...
  • Page 8 Chapter 1: AC701 Evaluation Board Features • Gen1 4-lane (x4) • Gen2 4-lane (x4) • SFP+ connector • 10/100/1,000 tri-speed Ethernet PHY • USB-to-UART bridge • High-Definition Multimedia Interface (HDMI™) technology codec • I2C bus • I2C MUX • I2C EEPROM (1 KB) •...
  • Page 9 AC701 Evaluation Kit product page. Caution! The AC701 board can be damaged by electrostatic discharge (ESD). Follow standard ESD prevention measures when handling the board. X-Ref Target - Figure 1-1 1 GB DDR3 Memory...

  • Page 10: Feature Descriptions

    Chapter 1: AC701 Evaluation Board Features Feature Descriptions Figure 1-2 shows the AC701 board. Each numbered feature that is referenced in Figure 1-2 is described in the sections that follow. Note: Figure 1-2 The image in is for reference only and might not reflect the current revision of the board.
  • Page 11 Feature Descriptions Table 1-1: AC701 Board Component Descriptions (Cont’d) Schematic Reference Callout Component Description Notes 0381502 Designator Page Number J25, J26 SMA GTP reference clock input Rosenberger 32K10K-400L5 Jitter attenuated clock (back side of Silicon Labs SI5324-C-GM board) GTP transceivers Embedded within FPGA U1 PCI Express®...

  • Page 12: Artix-7 Fpga

    For further information on Artix-7 FPGAs, see 7 Series FPGAs Overview (DS180) [Ref FPGA Configuration The AC701 board supports two of the five 7 series FPGA configuration modes: • Master SPI flash memory using the onboard Quad SPI flash memory •...
  • Page 13 Figure 1-4: Encryption Key Backup Circuit I/O Voltage Rails In addition to Bank 0, there are eight I/O banks available on the Artix-7 device. The voltages applied to the FPGA I/O banks used by the AC701 board are listed in Table 1-3.

  • Page 14: Ddr3 Memory Module

    Chapter 1: AC701 Evaluation Board Features Table 1-3: FPGA Bank Voltage Rails (Cont’d) Power Supply Rail U1 FPGA Bank Voltage Net Name Bank 34 FPGA_1V5 1.5V Bank 35 FPGA_1V5 1.5V DDR3 Memory Module [Figure 1-2, callout 2] The memory module at J1 is a 1 GB DDR3 small outline dual-inline memory module (SODIMM).
  • Page 15 SSTL15 DQ18 DDR3_D19 SSTL15 DQ19 DDR3_D20 SSTL15 DQ20 DDR3_D21 SSTL15 DQ21 DDR3_D22 SSTL15 DQ22 DDR3_D23 SSTL15 DQ23 DDR3_D24 SSTL15 DQ24 DDR3_D25 SSTL15 DQ25 DDR3_D26 SSTL15 DQ26 DDR3_D27 SSTL15 DQ27 AC701 Evaluation Board www.xilinx.com Send Feedback UG952 (v1.3) April 7, 2015...
  • Page 16 Chapter 1: AC701 Evaluation Board Features Table 1-4: DDR3 Memory Connections to the FPGA (Cont’d) J1 DDR3 Memory Schematic Net FPGA Pin (U1) I/O Standard Name Pin Number Pin Name DDR3_D28 SSTL15 DQ28 DDR3_D29 SSTL15 DQ29 DDR3_D30 SSTL15 DQ30 DDR3_D31...
  • Page 17 SSTL15 DQS5_N DDR3_DQS5_P SSTL15 DQS5_P DDR3_DQS6_N SSTL15 DQS6_N DDR3_DQS6_P SSTL15 DQS6_P DDR3_DQS7_N SSTL15 DQS7_N DDR3_DQS7_P SSTL15 DQS7_P DDR3_ODT0 SSTL15 ODT0 DDR3_ODT1 SSTL15 ODT1 DDR3_RESET_B LVCMOS15 RESET_B DDR3_S0_B SSTL15 S0_B AC701 Evaluation Board www.xilinx.com Send Feedback UG952 (v1.3) April 7, 2015...
  • Page 18 DDR3_CLK1_P DIFF_SSTL15 CK1_P The AC701 board DDR3 memory interface adheres to the constraints guidelines documented in the DDR3 Design Guidelines section of the 7 Series FPGAs Memory Interface 3]. The AC701 board DDR3 memory interface is a 40 Ω Solutions User Guide (UG586) [Ref impedance implementation.

  • Page 19: Quad Spi Flash Memory

    [Ref 5] provides details on using the Quad SPI flash memory. Figure 1-5 shows the connections of the Quad SPI flash memory on the AC701 board. For more details, see the Micron N25Q256A13ESF40G data sheet [Ref 15]. X-Ref Target - Figure 1-5...

  • Page 20: Spi Flash Memory External Programming Header

    Chapter 1: AC701 Evaluation Board Features SPI Flash Memory External Programming Header In addition to the Quad SPI device FPGA U1 connections shown in Table 1-5, the FPGA U1 SPI flash memory interface is connected to an external programming header J7.

  • Page 21: Sd Card Interface

    [Figure 1-2, callout 4] The AC701 board includes a secure digital input/output (SDIO) interface to provide user-logic access to general purpose nonvolatile SDIO memory cards and peripherals. The SD card slot is designed to support 50 MHz high speed SD cards.

  • Page 22: Usb Jtag Module

    UG952_c1_08_012913 Figure 1-8: JTAG Chain Block Diagram When an FMC card is attached to the AC701 board, it is automatically added to the JTAG chain through electronically controlled single-pole single-throw (SPST) switch U27. The SPST switch is in a normally closed state and transitions to an open state when an FMC card is attached.

  • Page 23: Clock Generation

    FPGA_TDI_BUF FPGA_TCK_BUF FPGA_TMS_BUF FPGA_TDO UG952_c1_09_101512 Figure 1-9: JTAG Circuit Clock Generation There are three clock sources available for the FPGA logic on the AC701 board (see Table 1-8). Table 1-8: AC701 Board Clock Sources FPGA Schematic Net Clock I/O Standard...
  • Page 24 Chapter 1: AC701 Evaluation Board Features Table 1-8: AC701 Board Clock Sources (Cont’d) FPGA Schematic Net Clock I/O Standard Description Pin (U1) Name Reference USER_CLOCK_P LVDS_25 Si570 3.3V LVDS I2C Programmable Oscillator (Silicon Labs). Default power-on frequency 156.250 MHz. See...
  • Page 25 [Figure 1-2, callout 6] The AC701 board has a 2.5V LVDS differential 200 MHz oscillator (U51) soldered onto the back side of the board and wired to an FPGA MRCC clock input on bank 34. This 200 MHz signal pair is named SYSCLK_P and SYSCLK_N, which are connected to FPGA U1 pins R3 and P3 respectively.
  • Page 26 Chapter 1: AC701 Evaluation Board Features The user clock circuit is shown in Figure 1-12. X-Ref Target - Figure 1-12 VCC3V3 VCC3V3 C192 0.01 μF 25V 4.7KΩ 5% Si570 Programmable Oscillator USER CLOCK SDA To I 2 C USER CLOCK N...
  • Page 27 GTP Transceiver Clock Multiplexer [Figure 1-2, callout 35] The AC701 board provides flexible GTP Quad 213 MGTREFCLK options through the use of external multiplexer (MUX) components U3 and U4 to service the GTP Quad 213 SFP, FMC, and SMA MGT interfaces.
  • Page 28 Chapter 1: AC701 Evaluation Board Features Table 1-9: MGT Clock Multiplexer U3 and U4 Clock Sources (Cont’d) Clock Name Reference Description SMA_MGT_REFCLK_P (net name). See U4 IN0: GTP Transceiver SMA Clock Input, page GTP SMA REFCLK (differential pair) SMA_MGT_REFCLK_N (net name). See...
  • Page 29 SEL1 MGT_CLK0_SEL1 MGT_CLK0_SEL0 VCC2V5 R454 1/10W NDS336P SFP_MGT_CLK_SEL0 460 mW R332 1/10W VCC2V5 R455 1/10W NDS336P SFP_MGT_CLK_SEL1 460 mW R333 1/10W UG952_c1_16_101612 Figure 1-15: MGT Clock Multiplexer U3 Circuit AC701 Evaluation Board www.xilinx.com Send Feedback UG952 (v1.3) April 7, 2015...
  • Page 30 Chapter 1: AC701 Evaluation Board Features Clock Multiplexer U4 SY89544UMG drives Bank 213 MGTREFCLK1 pins AA11 (P) and AB11(N). See Table 1-11 for clock Multiplexer U4 connections. Table 1-11: Multiplexer U4 SY89544UMG MGT Clock Inputs Clock Source SY89544UMG (U4) FPGA U1 Bank 213...
  • Page 31 SEL1 MGT_CLK1_SEL1 MGT_CLK1_SEL0 VCC2V5 R452 1/10W NDS336P PCIE_MGT_CLK_SEL0 460 mW R151 1/10W VCC2V5 R453 1/10W NDS336P PCIE_MGT_CLK_SEL1 460 mW R152 1/10W UG952_c1_17_101612 Figure 1-16: MGT Clock Multiplexer U4 Circuit AC701 Evaluation Board www.xilinx.com Send Feedback UG952 (v1.3) April 7, 2015...
  • Page 32 GND1 1.0M 5% EPHYCLK_Q0_C_N EPHYCLK_Q0_N EPHYCLK_XTAL_IN XTAL_IN GND2 R487 0Ω 5% C301 18pF 50V GND_EPHYCLK GND_EPHYCLK GND_EPHYCLK UG952_c1_13_101512 Figure 1-17: AC701 Board 125 MHz U3 MUX IN0 Source Circuit www.xilinx.com AC701 Evaluation Board Send Feedback UG952 (v1.3) April 7, 2015...
  • Page 33 [Figure 1-2, callout 10] The AC701 board includes a Silicon Labs Si5324 jitter attenuator U24 on the back side of the board. FPGA user logic can implement a clock recovery circuit and then output this clock to a differential I/O pair on I/O bank 16 (REC_CLOCK_C_P, FPGA U1 pin D23 and REC_CLOCK_C_N, FPGA U1 pin D24) for jitter attenuation.

  • Page 34: Gtp Transceivers

    [Figure 1-2, callout 9] The AC701 board includes a pair of SMA connectors for a GTP transceiver clock that are wired to GTP quad bank 213 through clock MUX U4. This differential clock has signal names SMA_MGT_REFCLK_P and SMA_REFCLK_N, which are connected to MGT clock MUX U4 input 0 pins 4 and 2 respectively.
  • Page 35 The GTP transceivers in 7 series FPGAs are grouped into four channels described as Quads. The reference clock for a Quad can be sourced from the Quad above or Quad below the GTP Quad of interest. There are two GTP transceiver Quads on the AC701 board with connectivity as shown here: •...
  • Page 36 Chapter 1: AC701 Evaluation Board Features Table 1-12: GTP Transceiver Interface Connections for FPGA U1 (Cont’d) Connected Transceiver Bank Placement Pin Name Schematic Net Name Connected Device Number GTP_BANK_216 GTPE2_CHANNEL_ MGTPTXP0_216 PCIE_TX3_P P1.A29 PCIe edge conn. P1 X0Y4 MGTPTXN0_216 PCIE_TX3_N P1.A30...

  • Page 37: Pci Express Edge Connector

    100Ω differential pair. The 7 series FPGAs GTP transceivers are used for multi-gigabit per second serial interfaces. The XC7A200T-2FBG676C FPGA (-2 speed grade) included with the AC701 board supports up to Gen2 x4. The PCIe clock is input from the edge connector. It is AC coupled to the FPGA through the MGTREFCLK0 pins of Quad 216.

  • Page 38: Sfp/Sfp+ Connector

    Chapter 1: AC701 Evaluation Board Features SFP/SFP+ Connector [Figure 1-2, callout 13] The AC701 board contains a small form-factor pluggable (SFP+) connector and cage assembly (P3) that accepts SFP or SFP+ modules. Figure 1-22 shows the SFP+ module connector circuitry.
  • Page 39 SFP_RS1 Jumper pins 1-2 = full transmitter bandwidth Jumper pins 2-3 = reduced transmitter bandwidth Test point J20 SFP_LOS High = loss of receiver signal Low = normal operation AC701 Evaluation Board www.xilinx.com Send Feedback UG952 (v1.3) April 7, 2015...

  • Page 40: 10/100/1000 Mb/S Tri-Speed Ethernet Phy

    [Figure 1-2, callout 14] The AC701 board uses the Marvell Alaska PHY device (88E1116R) at U12 for Ethernet communications at 10 Mb/s, 100 Mb/s, or 1,000 Mb/s. The board supports RGMII mode only. The PHY connection to a user-provided ethernet cable is through a Halo HFJ11-1G01E RJ-45 connector (P4) with built-in magnetics.
  • Page 41 X-Ref Target - Figure 1-23 C406 18pF 50V 25.00 MHz 50 ppm PHY_XTAL_OUT R275 GND1 1.0M 5% C405 GND2 PHY_XTAL_IN 18pF 50V UG952_c1_21_100312 Figure 1-23: Ethernet PHY Clock Source AC701 Evaluation Board www.xilinx.com Send Feedback UG952 (v1.3) April 7, 2015...

  • Page 42: Ethernet Phy User Leds

    USB cable is plugged into the USB port on the AC701 board. Xilinx UART IP is expected to be implemented in the FPGA logic. The FPGA supports the USB-to-UART bridge using four signal pins: Transmit (TX), Receive (RX), Request to Send (RTS), and Clear to Send (CTS).

  • Page 43: Hdmi Video Output

    [Figure 1-2, callout 17] The AC701 board provides a HDMI video output using the Analog Devices ADV7511KSTZ-P HDMI transmitter (U48). The HDMI output is provided on a Molex 500254-1927 HDMI type-A connector (P2). The ADV7511 is wired to support 1080P 60 Hz, YCbCr 4:4:4 encoding using 24-bit input data mapping.
  • Page 44 Chapter 1: AC701 Evaluation Board Features Figure 1-25 shows the HDMI codec circuit. X-Ref Target - Figure 1-25 VCC3V3 VCC1V8 VCC2V5 R104 R106 2.43K 2.43K SIT8102 R105 1/10W 1/10W 12.00000 MHZ 2.43K 50PPM 1/10W ADV7511 HDMI_INT HDMI_CEC_12MHZ_CLK IIC_SCL_HDMI CEC_CLK IIC_SDA_HDMI...
  • Page 45 HDMI_R_D32 LVCMOS18 HDMI_R_D33 LVCMOS18 HDMI_R_D34 LVCMOS18 HDMI_R_D35 LVCMOS18 AB26 HDMI_R_DE LVCMOS18 HDMI_R_SPDIF LVCMOS18 SPDIF HDMI_R_CLK LVCMOS18 AC26 HDMI_R_VSYNC LVCMOS18 VSYNC AA22 HDMI_R_HSYNC LVCMOS18 HSYNC HDMI_INT LVCMOS18 HDMI_SPDIF_OUT_LS LVCMOS18 SPDIF_OUT AC701 Evaluation Board www.xilinx.com Send Feedback UG952 (v1.3) April 7, 2015...

  • Page 46: Lcd Character Display

    Information about the ADV7511 is available on the Analog Devices website [Ref 16]. LCD Character Display [Figure 1-2, callout 18] A 2-line by 16-character display is provided on the AC701 board (Figure 1-26). X-Ref Target - Figure 1-26 LCD Display (16 x 2) UG952_c1_24_101612 Figure 1-26: LCD Display www.xilinx.com...
  • Page 47 UG952_c1_25_100312 Figure 1-27: LCD Interface Circuit The AC701 board base board uses a male Samtec MTLW-107-07-G-D-265 2x7 header (J23) with 0.025 inch square posts on 0.100 inch centers for connecting to a Samtec SLW-107-01-L-D female socket on the LCD display panel assembly. The LCD header...

  • Page 48: I2C Bus Switch

    [Figure 1-2, callout 19] The AC701 board implements a single I2C port on FPGA Bank 14 (IIC_SDA_MAIN, FPGA pin K25 and IIC_SCL_MAIN, FPGA pin N18), which is routed through a Texas Instruments PCA9548 1-to-8 channel I2C switch (U52). The I2C switch can operate at speeds up to 400 kHz.

  • Page 49: Ac701 Board Leds

    0b1010000, 0b0011000 Si5324 clock 0b1101000 Information about the PCA9548 is available on the TI Semiconductor website [Ref 22]. AC701 Board LEDs Table 1-23 lists all LEDs on the AC701 board. Table 1-23: AC701 Board LEDs Reference Schematic Description Notes Designator Page...

  • Page 50: User I/O

    Notes: 1. The Lumex SML-LX0603GW LED is green User I/O [Figure 1-2, callout – The AC701 board provides the following user and general purpose I/O capabilities: • Four user GPIO LEDs (callout 21) • GPIO_LED_[3-0]: DS5, DS4, DS3, DS2 •...
  • Page 51 GPIO SW W GPIO SW C GPIO SW E 4.7kΩ 4.7kΩ 4.7kΩ 0.1 W 0.1 W 0.1 W FPGA_1V5 GPIO SW S 4.7kΩ 0.1 W UG952_c1_29_011813 Figure 1-31: User Pushbuttons AC701 Evaluation Board www.xilinx.com Send Feedback UG952 (v1.3) April 7, 2015...
  • Page 52 Chapter 1: AC701 Evaluation Board Features Figure 1-32 shows the user CPU_RESET pushbutton switch circuit. X-Ref Target - Figure 1-32 FPGA_1V5 CPU_RESET 4.7kΩ 0.1 W UG952_c1_140_011813 Figure 1-32: CPU_RESET Pushbutton GPIO DIP Switch [Figure 1-2, callout 23] Figure 1-33 shows the GPIO DIP switch circuit.
  • Page 53 Figure 1-36: LCD Header J23 PMOD Connector Figure 1-37 shows the J48 PMOD male pin header. X-Ref Target - Figure 1-37 VCC3V3 PMOD_0 PMOD_1 PMOD_2 PMOD_3 HDR_1X6 UG952_c1_32_100412 Figure 1-37: PMOD Header J48 AC701 Evaluation Board www.xilinx.com Send Feedback UG952 (v1.3) April 7, 2015...
  • Page 54 Chapter 1: AC701 Evaluation Board Features Table 1-24 lists the GPIO Connections to FPGA U1. Table 1-24: GPIO Connections to FPGA U1 FPGA Pin (U1) Schematic Net Name I/O Standard GPIO Component Pin User LEDs (Active High) GPIO_LED_0 LVCMOS33 DS2.2...

  • Page 55: Switches

    [Figure 1-2, callout 26] The AC701 board power switch is SW15. Sliding the switch actuator from the Off to On position applies 12V power from J49, a 6-pin mini-fit connector. Green LED DS22 illuminates when the AC701 board power is on. See...
  • Page 56 FPGA_PROG_B UG952_c1_35_100412 Figure 1-40: FPGA_PROG_B Pushbutton SW9 Configuration Mode Switch SW1 The AC701 board supports two of the five 7 series FPGA configuration modes: • Master SPI flash memory using the onboard Quad SPI flash memory • JTAG using a standard-A to micro-B USB cable for connecting the host PC to the...

  • Page 57: Fpga Mezzanine Card Interface

    [Figure 1-2, callout 29] The AC701 board supports the VITA 57.1 FPGA mezzanine card (FMC) specification by providing high pin count (HPC) connector J30. HPC J30 is keyed so that a the mezzanine card faces away from the AC701 board when connected.
  • Page 58 2 differential clocks • 159 ground and 15 power connections Note: The AC701 board VADJ voltage for HPC connector J30 is determined by the FMC VADJ power sequencing logic described in Power Management, page Table 1-26: HPC Connections, J30 to FPGA U1...
  • Page 59 LVCMOS25 AD18 FMC1_HPC_HA12_P LVCMOS25 AC19 FMC1_HPC_HA16_P LVCMOS25 AE17 FMC1_HPC_HA12_N LVCMOS25 AD19 FMC1_HPC_HA16_N LVCMOS25 AF17 FMC1_HPC_HA15_P LVCMOS25 FMC1_HPC_HA20_P LVCMOS25 FMC1_HPC_HA15_N LVCMOS25 AA18 FMC1_HPC_HA20_N LVCMOS25 FMC1_HPC_HA19_P LVCMOS25 AC17 FMC1_HPC_HA19_N LVCMOS25 AD17 AC701 Evaluation Board www.xilinx.com Send Feedback UG952 (v1.3) April 7, 2015...
  • Page 60 Chapter 1: AC701 Evaluation Board Features Table 1-26: HPC Connections, J30 to FPGA U1 (Cont’d) J30 FMC1 FPGA J30 FMC1 FPGA Schematic Net Name I/O Standard Schematic Net Name I/O Standard HPC Pin (U1) Pin HPC Pin (U1) Pin VCCO_VADJ...

  • Page 61: Power Management

    [Figure 1-2, callout 30] The AC701 board uses power regulators and PMBus compliant system controllers from Texas Instruments to supply core and auxiliary voltages. The Texas Instruments Fusion Digital Power GUI is used to monitor the voltage and current levels of the board power modules.
  • Page 62 3.3V at 250 mA 1.5V/2=0.75V REFIN VTTDDR Source/Sink Regulator 3.3V POWER 0.75V at 3A 1.5V/2=0.75V REFIN DDR3_VTERM Source/Sink Regulator 3.3V POWER 0.75V at 3A UG952_c1_44_030915 Figure 1-42: AC701 Board Onboard Power Regulators www.xilinx.com AC701 Evaluation Board Send Feedback UG952 (v1.3) April 7, 2015...
  • Page 63 2.0 PCB, 0431747-xx. 5. TPS84621RUQ adjustable linear regulator was on AC701 boards previous to board Rev. 2.0. Previous board revisions are identified by an assembly number label affixed to each pre-rev 2.0 PCB, 0431747-xx. 6. TPS84620RUQ linear regulator was on AC701 boards previous to board Rev.
  • Page 64 Chapter 1: AC701 Evaluation Board Features Monitoring Voltage and Current Voltage and current monitoring and voltage control are available for the TI controlled power rails through the Texas Instruments Fusion Digital Power Designer GUI. The two onboard TI UCD90120A power controllers (U8 at PMBus address 101 and U9 at address 102) are wired to the same PMBus.
  • Page 65 Feature Descriptions VCCO_VADJ Voltage Control The FMC VCCO_VADJ rail is set to 2.5V. When the AC701 board is powered on, the state of the FMC_VADJ_ON_B signal wired to header J8 is sampled by the TI UCD90120A controller U9. If a jumper is installed on J8, signal FMC_VADJ_ON_B is held low, and TI controller U9 energizes the FMC VCCO_VADJ rail at power on.

  • Page 66: Ac701 Board Power System

    UG952_c1_38_100512 Figure 1-43: FPGA Cooling Fan Circuit AC701 Board Power System The AC701 board hosts a power system based on the Texas Instruments (TI) UCD90120A power supply sequencer and monitor, and the LMZ31500 and LMZ31700 family voltage regulators. UCD90120A Description The UCD90120A is a 12-rail PMBus/I2C addressable power-supply sequencer and monitor.
  • Page 67 The sync input allows synchronization over the 200 kHz to 1200 kHz switching frequency range and up to six modules can be connected in parallel for higher load currents. Table 1-31 shows the AC701 board power system configuration for controller U8. Table 1-31: Controller U8 Power System Configuration Schematic Sequencer...
  • Page 68 Chapter 1: AC701 Evaluation Board Features Figure 1-44 shows the power system for UCD90120A U8 controller #1 X-Ref Target - Figure 1-44 U49 (1.0V Nom) LMZ31710 Rs 5mΩ UCD90120A Vout VCCINT 1.0V +12V Controller Input Filter (Controller 1) Rail Enable...
  • Page 69 Feature Descriptions Table 1-32 shows the AC701 TI power system configuration for controller U9. Table 1-32: Controller U9 Power System Configuration Schematic Sequencer Regulator Type Voltage Current Page Page Contents Net Name UCD90120A #2 Addr 102, Rail 1 VCCO_VADJ LMZ31506 (U56) 2.5V...
  • Page 70 Chapter 1: AC701 Evaluation Board Features Figure 1-45 shows the power system for UCD90120A U9 controller #2 rails 1 through 5. X-Ref Target - Figure 1-45 U56 (2.5V Nom) Notes: 1. Capacitors labled C f are bulk filter capacitors. LMZ31506 Rs 5mΩ...

  • Page 71: Xadc Power System Measurement

    The LMZ31503 and LMZ31700 family adjustable voltage regulators have their output voltage set by an external resistor. The regulator topology on the AC701 board permits the UCD90120A to monitor rail voltage and current. Voltage margining at +5% and -5% is also implemented.
  • Page 72 Chapter 1: AC701 Evaluation Board Features Figure 1-46 shows the XADC external multiplexer block diagram. X-Ref Target - Figure 1-46 FPGA_1V5_SENSE_P 1.00 K FPGA_1V5_XADC_P (1.5V Scaled to 0.75V) 1.00 K FPGA_1V5_XADC_N VCCO_VADJ_SENSE_P 3.01 K ADG707BRU VCCO_VADJ_XADC_P VCCINT_XADC_CS_P/N S1A/B (2.5V Scaled to 0.625V) VCCAUX_XADC_CS_P/N 1.00 K...
  • Page 73 Feature Descriptions Table 1-33 Table 1-34 list the AC701 board XADC power system voltage and current measurement details for the external MUXes U14 and U13. Table 1-33: XADC Measurements through Mux U14 Op Amp 8-to-1 Multiplexer U14 sense Measurement Rail...
  • Page 74 Chapter 1: AC701 Evaluation Board Features Table 1-34: XADC Measurements through Mux U13 (Cont’d) Op Amp 8-to-1 Multiplexer U14 sense Measurement Rail Current Schematic Type Name Range Reference Net Name A[2:0] Gain Range Designator Number Name MGTAVTT_XADC_CS_P MGTAVTT CS 0A-1.5A 0V-0.756V...

  • Page 75: Xadc Header

    100Ω UG952_c1_39_101612 Figure 1-47: Header XADC_VREF Voltage Source Options The AC701 board supports both the internal FPGA sensor measurements and the external measurement capabilities of the XADC. Internal measurements of the die temperature, , and V are available. The AC701 board V...
  • Page 76 Chapter 1: AC701 Evaluation Board Features For external measurements, an XADC header (J19) is provided. This header can be used to provide analog inputs to the FPGA dedicated VP/VN channel, and to the VAUXP[0]/ VAUXN[0], VAUXP[8]/VAUXN[8] auxiliary analog input channels. Simultaneous sampling of Channel 0 and Channel 8 is supported.

  • Page 77: Configuration Options

    Configuration Options Configuration Options The FPGA on the AC701 board can be configured using these methods: • Master SPI flash memory (uses the Quad SPI flash memory U7). • JTAG (uses the U26 Digilent USB-to-JTAG bridge or J4 download cable connector).
  • Page 78 DONE DS10 D[3:0] GREEN Bank 14 FCS_B N25Q256A13ESF40G QUAD SPI DQ[1:0] DQ2_WP DQ3_HOLD_B Oscillator EMCCLK 90 MHz SIT8103 UG952_c1_42_072513 Figure 1-50: AC701 Board Quad SPI Flash Memory Configuration Circuit www.xilinx.com AC701 Evaluation Board Send Feedback UG952 (v1.3) April 7, 2015...

  • Page 79: Appendix A: Default Switch And Jumper Settings

    ON Position = 1 2 3 4 OFF Position = 0 UG952_aA_01_100712 Figure A-1: SW2 Default Settings Table A-1: SW2 Default Switch Settings Position Function Default GPIO_DIP_SW0 GPIO_DIP_SW1 GPIO_DIP_SW2 GPIO_DIP_SW3 AC701 Evaluation Board www.xilinx.com Send Feedback UG952 (v1.3) April 7, 2015...

  • Page 80: Configuration Dip Switch Sw1

    Figure A-2: SW1 Default Settings The default mode setting M[2:0] = 001 selects Master SPI flash memory configuration at board power-on. Table A-2: SW1 Default Switch Settings Position Function Default FPGA_M2 FPGA_M1 FPGA_M0 www.xilinx.com AC701 Evaluation Board Send Feedback UG952 (v1.3) April 7, 2015...

  • Page 81: Default Jumper Settings

    Default Jumper Settings Default Jumper Settings The AC701 board default jumper configurations are listed in Table A-3. The AC701 board jumper header locations are shown in Figure A-3. Table A-3: AC701 Default Jumper Settings Header Ref Jumper Schematic Callout Description...
  • Page 82 Appendix A: Default Switch and Jumper Settings X-Ref Target - Figure A-3 Figure A-3: AC701 Board Components (Rev. 2.0) www.xilinx.com AC701 Evaluation Board Send Feedback UG952 (v1.3) April 7, 2015...

  • Page 83: Appendix B: Vita 57.1 Fmc Connector Pinouts

    Figure B-1 shows the pinout of the FPGA mezzanine card (FMC) high pin count (HPC) connector defined by the VITA 57.1 FMC specification. For a description of how the AC701 board implements the FMC specification, see FPGA Mezzanine Card Interface, page 57...
  • Page 84 Appendix B: VITA 57.1 FMC Connector Pinouts www.xilinx.com AC701 Evaluation Board Send Feedback UG952 (v1.3) April 7, 2015...

  • Page 85: Appendix C: Master Constraints File Listing

    Appendix C Master Constraints File Listing TheAC701 board master Xilinx Design Constraints (XDC) file template provides for designs targeting the AC701 board. Net names in the constraints listed in the AC701 Board XDC File Listing correlate with net names on the AC701 board schematic. You must identify the appropriate pins and replace the net names in this list with net names in the user RTL.
  • Page 86 PACKAGE_PIN B5 [get_ports DDR3_DQS5_P] set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS5_P] set_property PACKAGE_PIN A5 [get_ports DDR3_DQS5_N] set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS5_N] set_property PACKAGE_PIN C1 [get_ports DDR3_DQS4_P] set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS4_P] www.xilinx.com AC701 Evaluation Board Send Feedback UG952 (v1.3) April 7, 2015...
  • Page 87 AC701 Board XDC File Listing set_property PACKAGE_PIN B1 [get_ports DDR3_DQS4_N] set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS4_N] set_property PACKAGE_PIN V3 [get_ports DDR3_DQS3_P] set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS3_P] set_property PACKAGE_PIN V2 [get_ports DDR3_DQS3_N] set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS3_N] set_property PACKAGE_PIN AD1 [get_ports DDR3_DQS2_P]...
  • Page 88 PACKAGE_PIN W6 [get_ports DDR3_D26] set_property IOSTANDARD SSTL15 [get_ports DDR3_D26] set_property PACKAGE_PIN W3 [get_ports DDR3_D25] set_property IOSTANDARD SSTL15 [get_ports DDR3_D25] set_property PACKAGE_PIN Y3 [get_ports DDR3_D24] set_property IOSTANDARD SSTL15 [get_ports DDR3_D24] www.xilinx.com AC701 Evaluation Board Send Feedback UG952 (v1.3) April 7, 2015...
  • Page 89 AC701 Board XDC File Listing set_property PACKAGE_PIN AB1 [get_ports DDR3_D23] set_property IOSTANDARD SSTL15 [get_ports DDR3_D23] set_property PACKAGE_PIN AC1 [get_ports DDR3_D22] set_property IOSTANDARD SSTL15 [get_ports DDR3_D22] set_property PACKAGE_PIN Y2 [get_ports DDR3_D21] set_property IOSTANDARD SSTL15 [get_ports DDR3_D21] set_property PACKAGE_PIN Y1 [get_ports DDR3_D20]...
  • Page 90 PACKAGE_PIN M20 [get_ports PCIE_PERST] set_property IOSTANDARD LVCMOS33 [get_ports PCIE_PERST] set_property PACKAGE_PIN F11 [get_ports PCIE_CLK_QO_P] set_property IOSTANDARD LVDS_25 [get_ports PCIE_CLK_QO_P] set_property PACKAGE_PIN E11 [get_ports PCIE_CLK_QO_N] set_property IOSTANDARD LVDS_25 [get_ports PCIE_CLK_QO_N] www.xilinx.com AC701 Evaluation Board Send Feedback UG952 (v1.3) April 7, 2015...
  • Page 91 AC701 Board XDC File Listing #GPIO LCD set_property PACKAGE_PIN L22 [get_ports LCD_DB7_LS] set_property IOSTANDARD LVCMOS33 [get_ports LCD_DB7_LS] set_property PACKAGE_PIN M25 [get_ports LCD_DB6_LS] set_property IOSTANDARD LVCMOS33 [get_ports LCD_DB6_LS] set_property PACKAGE_PIN M24 [get_ports LCD_DB5_LS] set_property IOSTANDARD LVCMOS33 [get_ports LCD_DB5_LS] set_property PACKAGE_PIN L25...
  • Page 92 PACKAGE_PIN A23 [get_ports XADC_MUX_ADDR2_LS] set_property IOSTANDARD LVCMOS25 [get_ports XADC_MUX_ADDR2_LS] set_property PACKAGE_PIN L19 [get_ports XADC_GPIO_3] set_property IOSTANDARD LVCMOS25 [get_ports XADC_GPIO_3] set_property PACKAGE_PIN K18 [get_ports XADC_GPIO_2] set_property IOSTANDARD LVCMOS25 [get_ports XADC_GPIO_2] www.xilinx.com AC701 Evaluation Board Send Feedback UG952 (v1.3) April 7, 2015...
  • Page 93 AC701 Board XDC File Listing set_property PACKAGE_PIN E22 [get_ports XADC_GPIO_1] set_property IOSTANDARD LVCMOS25 [get_ports XADC_GPIO_1] set_property PACKAGE_PIN H17 [get_ports XADC_GPIO_0] set_property IOSTANDARD LVCMOS25 [get_ports XADC_GPIO_0] #FAN set_property PACKAGE_PIN J25 [get_ports SM_FAN_TACH] set_property IOSTANDARD LVCMOS25 [get_ports SM_FAN_TACH] set_property PACKAGE_PIN J26 [get_ports SM_FAN_PWM]...
  • Page 94 PACKAGE_PIN A22 [get_ports FMC1_HPC_LA15_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA15_N] set_property PACKAGE_PIN E21 [get_ports FMC1_HPC_LA16_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA16_P] set_property PACKAGE_PIN D21 [get_ports FMC1_HPC_LA16_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA16_N] www.xilinx.com AC701 Evaluation Board Send Feedback UG952 (v1.3) April 7, 2015...
  • Page 95 AC701 Board XDC File Listing set_property PACKAGE_PIN K21 [get_ports FMC1_HPC_LA17_CC_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA17_CC_P] set_property PACKAGE_PIN J21 [get_ports FMC1_HPC_LA17_CC_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA17_CC_N] set_property PACKAGE_PIN G20 [get_ports FMC1_HPC_LA18_CC_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA18_CC_P] set_property PACKAGE_PIN G21 [get_ports FMC1_HPC_LA18_CC_N]...
  • Page 96 PACKAGE_PIN AF22 [get_ports FMC1_HPC_HA10_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA10_N] set_property PACKAGE_PIN AD20 [get_ports FMC1_HPC_HA11_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA11_P] set_property PACKAGE_PIN AE20 [get_ports FMC1_HPC_HA11_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA11_N] www.xilinx.com AC701 Evaluation Board Send Feedback UG952 (v1.3) April 7, 2015...
  • Page 97 AC701 Board XDC File Listing set_property PACKAGE_PIN AC19 [get_ports FMC1_HPC_HA12_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA12_P] set_property PACKAGE_PIN AD19 [get_ports FMC1_HPC_HA12_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA12_N] set_property PACKAGE_PIN AC18 [get_ports FMC1_HPC_HA13_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA13_P] set_property PACKAGE_PIN AD18 [get_ports FMC1_HPC_HA13_N]...
  • Page 98 PACKAGE_PIN T20 [get_ports HDMI_SPDIF_OUT_LS] set_property IOSTANDARD LVCMOS18 [get_ports HDMI_SPDIF_OUT_LS] #ETHERNET set_property PACKAGE_PIN U22 [get_ports PHY_TX_CLK] set_property IOSTANDARD LVCMOS18 [get_ports PHY_TX_CLK] set_property PACKAGE_PIN U21 [get_ports PHY_RX_CLK] set_property IOSTANDARD LVCMOS18 [get_ports PHY_RX_CLK] www.xilinx.com AC701 Evaluation Board Send Feedback UG952 (v1.3) April 7, 2015...
  • Page 99 AC701 Board XDC File Listing set_property PACKAGE_PIN V18 [get_ports PHY_RESET_B] set_property IOSTANDARD LVCMOS18 [get_ports PHY_RESET_B] set_property PACKAGE_PIN W18 [get_ports PHY_MDC] set_property IOSTANDARD LVCMOS18 [get_ports PHY_MDC] set_property PACKAGE_PIN T14 [get_ports PHY_MDIO] set_property IOSTANDARD LVCMOS18 [get_ports PHY_MDIO] set_property PACKAGE_PIN T15 [get_ports PHY_TX_CTRL]...
  • Page 100 Appendix C: Master Constraints File Listing set_property IOSTANDARD LVDS_25 [get_ports SFP_MGT_CLK1_P] set_property PACKAGE_PIN AB11 [get_ports SFP_MGT_CLK1_N] set_property IOSTANDARD LVDS_25 [get_ports SFP_MGT_CLK1_N] www.xilinx.com AC701 Evaluation Board Send Feedback UG952 (v1.3) April 7, 2015...

  • Page 101: Appendix D: Board Setup

    Installation of the AC701 board inside a computer chassis is required when developing or testing PCI Express® functionality. When the AC701 board is used inside a computer chassis (that is, plugged in to the PCIe® slot), power is provided from the ATX power supply 4-pin peripheral connector through...
  • Page 102 Appendix D: Board Setup Slide the AC701 board power switch SW15 to the ON position. The PC can now be powered on. www.xilinx.com AC701 Evaluation Board Send Feedback UG952 (v1.3) April 7, 2015...

  • Page 103: Appendix E: Board Specifications

    Board Specifications Dimensions Height 5.5 in. (14.0 cm) Length 10.5 in. (26.7 cm) Note: The AC701 board height exceeds the standard 4.376 in. (11.15 cm) height of a PCI Express card. Environmental Temperature Operating: 0°C to +45°C Storage: –25°C to +60°C...
  • Page 104 Appendix E: Board Specifications www.xilinx.com AC701 Evaluation Board Send Feedback UG952 (v1.3) April 7, 2015...

  • Page 105: Appendix F: Additional Resources

    Topics include design assistance, advisories, and troubleshooting tips. References The most up to date information related to the AC701 board and its documentation is available on the following websites. Artix-7 FPGA AC701 Evaluation Kit website...
  • Page 106 Appendix F: Additional Resources 14. AC701 Si570 Fixed Frequencies (XTP229) Documents associated with other devices used by the AC701 board are available at these vendor websites: 15. Micron Technology: www.micron.com (N25Q256A13ESF40G, MT8JTF12864HZ-1G6G1 ) 16. Analog Devices: www.analog.com/en/index (ADV7511KSTZ-P) 17. Integrated Device Technology: www.idt.com...

  • Page 107: Appendix G: Regulatory And Compliance Information

    This product is designed and tested to conform to the European Union directives and standards described in this section. Refer to the Artix-7 FPGA AC701 Evaluation Kit Master Answer Record (AR 51900) concerning the CE requirements for the PC test environment. Declaration of Conformity Artix-7 FPGA AC701 Declaration of Conformity is online.

  • Page 108: Markings

    This product complies with Directive 2002/95/EC on the restriction of hazardous substances (RoHS) in electrical and electronic equipment. This product complies with CE Directives 2006/95/EC, Low Voltage Directive (LVD) and 2004/108/EC, Electromagnetic Compatibility (EMC) Directive. www.xilinx.com AC701 Evaluation Board Send Feedback UG952 (v1.3) April 7, 2015...

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