Xilinx AC701 User Manual page 30

Chapter 1: AC701 Evaluation Board Features
X-Ref Target - Figure 1-17
EPHYCLK_Q0_P
EPHYCLK_Q0_N
SI5324_OUT0_C_P
SI5324_OUT0_C_N
FMC1_HBC_GBTCLK0_M2C_C_P
FMC1_HBC_GBTCLK0_M2C_C_N
SFP_MGT_CLK_SEL0
SFP_MGT_CLK_SEL1
30
VCC2V5
SY89544UMG
1
VCC1
5
VCC2
4
IN0
50
3
NC VT0
50
2
IN0
32
IN1
50
31
NC VT1
50
30
IN1
27
IN2
50
26
NC VT2
50
25
IN2
23
NC IN3
50
22
NC VT3
50
21
NC IN3
6
SEL0
19
SEL1
MGT_CLK0_SEL1
MGT_CLK0_SEL0
R332
10K
1/10W
1%
R333
10K
1/10W
1%
Figure 1-17: MGT Clock MUX U3 Circuit
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U3
VCC3
VCC4
VCC5
0
VCC6
VCC7
VCC8
1
Q
Q
GND1
2
GND2
GND3
GND4
3
S1
GND5
S0
GND6
PWRPAD
VCC2V5
R454
10K
1/10W
1%
Q24
NDS336P
460 mW
GND
VCC2V5
R455
10K
1/10W
1%
Q25
NDS336P
460 mW
GND
VCC2V5
C105
8
0.1µF
25V
17
X5R
20
GND
24
C320
28
0.1µF
25V
29
X5R
10 SFP_MGT_CLK0_P
SFP_MGT_CLK0_P
11
7
C318
TO MGT BANK 213
0.1µF
MGTREFCLK0_P/N
9
PINS AA13, AB13
25V
X5R
12
13
16
18
33
GND
UG952_c1_16_101612
AC701 Evaluation Board
UG952 (v1.2) August 28, 2013