Xilinx AC701 User Manual page 33

Table 1-12
Table 1-12: GTP Interface Connections for FPGA U1
Transceiver Bank Placement
GTP_BANK_213 GTPE2_CHANNEL_
X0Y0
GTPE2_CHANNEL_
X0Y1
GTPE2_CHANNEL_
X0Y2
GTPE2_CHANNEL_
X0Y3
GTPE2_CHANNEL_
X0Y0
AC701 Evaluation Board
UG952 (v1.2) August 28, 2013
lists the GTP interface connections to the FPGA (U1).
Pin
Pin Name
Number
AC10 MGTPTXP0_213
AD10 MGTPTXN0_213
AC12 MGTPRXP0_213
AD12 MGTPRXN0_213
AE9 MGTPTXP1_213
AF9 MGTPTXN1_213
AE13 MGTPRXP1_213
AF13 MGTPRXN1_213
AC8 MGTPTXP2_213
AD8 MGTPTXN2_213
AC14 MGTPRXP2_213
AD14 MGTPRXN2_213
AE7 MGTPTXP3_213
AF7 MGTPTXN3_213
AE11 MGTPRXP3_213
AF11 MGTPRXN3_213
AA13 MGTREFCLK0P_213
AB13 MGTREFCLK0N_213
AA11 MGTREFCLK1P_213
AB11 MGTREFCLK1N_213
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Connected
Schematic Net Name
SFP_TX_P
SFP_TX_N
SFP_RX_P
SFP_RX_N
FMC1_HPC_DP0_C2M_P J30.C2
FMC1_HPC_DP0_C2M_N J30.C3
FMC1_HPC_DP0_M2C_P J30.C6
FMC1_HPC_DP0_M2C_N J30.C7
FMC1_HPC_DP1_C2M_P J30.A22
FMC1_HPC_DP1_C2M_N J30.A23
FMC1_HPC_DP1_M2C_P J30.A2
FMC1_HPC_DP1_M2C_N J30.A3
SMA_MGT_TX_P
SMA_MGT_TX_N
SMA_MGT_RX_P
SMA_MGT_RX_N
SFP_MGT_CLK0_C_P U3.10
SFP_MGT_CLK0_C_N U3.11
SFP_MGT_CLK1_C_P U4.10
SFP_MGT_CLK1_C_N U4.11
Feature Descriptions
Connected Device
Pin
P3.18 SFP+ Conn. P3
P3.19 SFP+ Conn. P3
P3.13 SFP+ Conn. P3
P3.12 SFP+ Conn. P3
FMC HPC J30
FMC HPC J30
FMC HPC J30
FMC HPC J30
FMC HPC J30
FMC HPC J30
FMC HPC J30
FMC HPC J30
J44.1 Clock Input SMA
J45.1 Clock Input SMA
J46.1 Clock Input SMA
J47.1 Clock Input SMA
(1)
Clock Mux U3
(1)
Clock Mux U3
(1)
Clock Mux U4
(1)
Clock Mux U4
33