Xilinx AC701 User Manual page 95

AC701 Evaluation Board
UG952 (v1.2) August 28, 2013
set_property IOSTANDARD SSTL15 [get_ports DDR3_S1_B]
set_property PACKAGE_PIN R2 [get_ports DDR3_ODT0]
set_property IOSTANDARD SSTL15 [get_ports DDR3_ODT0]
set_property PACKAGE_PIN U2 [get_ports DDR3_ODT1]
set_property IOSTANDARD SSTL15 [get_ports DDR3_ODT1]
set_property PACKAGE_PIN U1 [get_ports DDR3_TEMP_EVENT]
set_property IOSTANDARD LVCMOS15 [get_ports DDR3_TEMP_EVENT]
set_property PACKAGE_PIN AC6 [get_ports DDR3_DM0]
set_property IOSTANDARD SSTL15 [get_ports DDR3_DM0]
set_property PACKAGE_PIN AC4 [get_ports DDR3_DM1]
set_property IOSTANDARD SSTL15 [get_ports DDR3_DM1]
set_property PACKAGE_PIN AA3 [get_ports DDR3_DM2]
set_property IOSTANDARD SSTL15 [get_ports DDR3_DM2]
set_property PACKAGE_PIN U7 [get_ports DDR3_DM3]
set_property IOSTANDARD SSTL15 [get_ports DDR3_DM3]
set_property PACKAGE_PIN G1 [get_ports DDR3_DM4]
set_property IOSTANDARD SSTL15 [get_ports DDR3_DM4]
set_property PACKAGE_PIN F3 [get_ports DDR3_DM5]
set_property IOSTANDARD SSTL15 [get_ports DDR3_DM5]
set_property PACKAGE_PIN G5 [get_ports DDR3_DM6]
set_property IOSTANDARD SSTL15 [get_ports DDR3_DM6]
set_property PACKAGE_PIN H9 [get_ports DDR3_DM7]
set_property IOSTANDARD SSTL15 [get_ports DDR3_DM7]
set_property PACKAGE_PIN V8 [get_ports DDR3_DQS0_P]
set_property IOSTANDARD SSTL15 [get_ports DDR3_DQS0_P]
set_property PACKAGE_PIN W8 [get_ports DDR3_DQS0_N]
set_property IOSTANDARD SSTL15 [get_ports DDR3_DQS0_N]
set_property PACKAGE_PIN AD5 [get_ports DDR3_DQS1_P]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS1_P]
set_property PACKAGE_PIN AE5 [get_ports DDR3_DQS1_N]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS1_N]
set_property PACKAGE_PIN AD1 [get_ports DDR3_DQS2_P]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS2_P]
set_property PACKAGE_PIN AE1 [get_ports DDR3_DQS2_N]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS2_N]
set_property PACKAGE_PIN V3 [get_ports DDR3_DQS3_P]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS3_P]
set_property PACKAGE_PIN V2 [get_ports DDR3_DQS3_N]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS3_N]
set_property PACKAGE_PIN C1 [get_ports DDR3_DQS4_P]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS4_P]
set_property PACKAGE_PIN B1 [get_ports DDR3_DQS4_N]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS4_N]
set_property PACKAGE_PIN B5 [get_ports DDR3_DQS5_P]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS5_P]
set_property PACKAGE_PIN A5 [get_ports DDR3_DQS5_N]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS5_N]
set_property PACKAGE_PIN J4 [get_ports DDR3_DQS6_P]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS6_P]
set_property PACKAGE_PIN H4 [get_ports DDR3_DQS6_N]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS6_N]
set_property PACKAGE_PIN H7 [get_ports DDR3_DQS7_P]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS7_P]
set_property PACKAGE_PIN G7 [get_ports DDR3_DQS7_N]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS7_N]
set_property PACKAGE_PIN AB6 [get_ports DDR3_D0]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D0]
set_property PACKAGE_PIN AA8 [get_ports DDR3_D1]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D1]
set_property PACKAGE_PIN Y8 [get_ports DDR3_D2]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D2]
set_property PACKAGE_PIN AB5 [get_ports DDR3_D3]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D3]
set_property PACKAGE_PIN AA5 [get_ports DDR3_D4]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D4]
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AC701 Board XDC File Listing
95