Xilinx AC701 User Manual page 23

System Clock Source
[Figure
The AC701 board has a 2.5V LVDS differential 200 MHz oscillator (U51) soldered onto the
back side of the board and wired to an FPGA MRCC clock input on bank 34. This 200 MHz
signal pair is named SYSCLK_P and SYSCLK_N, which are connected to FPGA U1 pins R3
and P3 respectively.
•
•
•
For more details, see the Si Time SiT9102 data sheet
shown in
X-Ref Target - Figure 1-11
AC701 Evaluation Board
UG952 (v1.2) August 28, 2013
1-2, callout 6]
Oscillator: Si Time SiT9102AI-243N25E200.00000 (200 MHz)
PPM frequency jitter: 50 ppm
Differential Output
Figure 1-11.
C30
0.1 µF 10V
X5R
GND
Figure 1-11: System Clock Source
www.xilinx.com
[Ref
VCC2V5
U51
SIT9102
200 MHz
Oscillator
1 6
OE VCC
2 5
NC OUT_B
3 4
GND OUT
Feature Descriptions
6]. The system clock circuit is
SYSCLK_N
R166
100Ω 1%
SYSCLK_P
UG952_c1_10_100212
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