Xilinx AC701 User Manual page 10

Chapter 1: AC701 Evaluation Board Features
Each configuration interface corresponds to one or more configuration modes and bus
widths as listed in
2, and 3 respectively as shown in
X-Ref Target - Figure 1-3
The default mode setting is M[2:0] = 001, which selects Master SPI at board power-on.
Refer to the
SW1.
Table 1-2: AC701 Board FPGA Configuration Modes
For full details on configuring the FPGA, see UG470, 7 Series FPGAs Configuration User
Guide
Encryption Key Backup Circuit
FPGA U1 implements bitstream encryption key technology. The AC701 board provides the
encryption key backup battery circuit shown in
button-type battery B1 is soldered to the board with the positive output connected to
FPGA U1 VCCBATT pin G14. The battery supply current I
when board power is off. B1 is charged from the VCC1V8 1.8V rail through a series diode
with a typical forward voltage drop of 0.38V. and 4.7 KΩ current limit resistor. The nominal
charging voltage is 1.62V.
10
Table 1-2. The mode switches M2, M1, and M0 are on SW1 positions 1,
FPGA_M2
FPGA_M1
FPGA_M0
Configuration Options, page 77
Configuration SW1 DIP switch
Mode Settings (M[2:0])
Master SPI
JTAG
www.xilinx.com
Figure 1-3.
R339 R338 R337
1.21K 1% 1.21K 1% 1.21K 1%
1/10W 1/10W 1/10W
Figure 1-3: SW1 Default Settings
for more information about the mode switch
001
101
Figure
FPGA_3V3
SW1
1 6
NC 2 5
3 4
SDA03H1SBD
UG952_c1_03_011713
Bus CCLK
Width Direction
x1, x2, x4 Output
x1 Not Applicable
1-4. The rechargeable 1.5V lithium
specification is 150 nA max
BATT
AC701 Evaluation Board
UG952 (v1.2) August 28, 2013