Xilinx AC701 User Manual page 37

Table 1-13
Table 1-13: FPGA U1 to SFP+ Module Connections
Table 1-14
Table 1-14: SFP+ Module Control and Status
AC701 Evaluation Board
UG952 (v1.2) August 28, 2013
lists the SFP+ module RX and TX connections to the FPGA.
FPGA Pin Schematic
(U1) Net Name
AD12 SFP_RX_N
AC12 SFP_RX_P
AD10 SFP_TX_N
AC10 SFP_TX_P
R18 SFP_TX_DISABLE
R23 SFP_LOS
lists the SFP+ module control and status connections.
SFP Control/Status
Signal
SFP_TX_FAULT Test Point J22
High = Fault
Low = Normal Operation
SFP_TX_DISABLE Jumper J6 (and FPGA pin R18)
Off = SFP Disabled
On = SFP Enabled
SFP_MOD_DETECT Test Point J21
High = Module Not Present
Low = Module Present
SFP_RS0 Jumper J38
Jumper Pins 1-2 = Full RX Bandwidth
Jumper Pins 2-3 = Reduced RX Bandwidth
SFP_RS1 Jumper J39
Jumper Pins 1-2 = Full TX Bandwidth
Jumper Pins 2-3 = Reduced TX Bandwidth
SFP_LOS Test Point J20
High = Loss of Receiver Signal
Low = Normal Operation
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SFP+ Pin SFP+ Pin Name
(P5)
12
13
19
18
3
8
Board Connection
Feature Descriptions
(P5)
RD_N
RD_P
TD_N
TD_P
TX_DISABLE
LOS
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