Xilinx AC701 User Manual page 65

Figure 1-42
X-Ref Target - Figure 1-42
Notes:
U9
1. Capacitors labled C f are bulk filter capacitors.
UCD90120A
2. Voltage Sense is connected
at point of load.
Controller
(Controller 2)
Rail Enable
GPIO (Out)
PWM Margin
FPWM (Out)
Current Sense
ADC (In)
Voltage Sense
ADC (In)
FMC_ADJ_SEL[1:0]
GPIO (Out)
FMC_ADJ_SEL[1:0]
Value
0 0
0 1
1 0
1 1
Rail Enable
GPIO (Out)
PWM Margin
FPWM (Out)
Current Sense
ADC (In)
Voltage Sense
ADC (In)
Rail Enable
GPIO (Out)
PWM Margin
FPWM (Out)
Current Sense
ADC (In)
Voltage Sense
ADC (In)
Rail Enable
GPIO (Out)
PWM Margin
FPWM (Out)
Current Sense
ADC (In)
Voltage Sense
ADC (In)
Rail Enable
GPIO (Out)
PWM Margin
FPWM (Out)
Current Sense
ADC (In)
Voltage Sense
ADC (In)
AC701 Evaluation Board
UG952 (v1.2) August 28, 2013
shows the power system for UCD90120A U9 controller #2 rails 1 through 5.
+12V
(2)
VCCO_ADJ
Output
2.5V
1.8V
3.3V
+12V
3.3V
(2)
+12V
(2)
+12V
(2)
+12V
(2)
Figure 1-42: U9 Controller #2 UCD90120A Power System
www.xilinx.com
U49 (2.5V Nom)
TPS84621
Vin Vout
Input
C f
Filter
EN
V
fb
FB
I0B
U64
YB
I1B
S[1:0]
I2B
I3B
U57 (1.8V Nom)
TPS84320
Vin Vout
Input
C f
Filter
EN
V
fb
FB
U58 (3.3V Nom)
TPS84321
Vin Vout
Input
C f
Filter
EN
V
fb
FB
U59 (1.0V Nom)
TPS84320
Vin Vout
Input
C f
Filter
EN
V
fb
FB
U60 (1.2V Nom)
TPS84320
Vin Vout
Input
C f
Filter
EN
V
fb
FB
Feature Descriptions
Rs 5mΩ
VCCO_ADJ 2.5V
(1)
C f
G = 125.07
VCCO_VADJ
0A-3.2A
CS = 0V-2.00V
VCC1V8 1.8V
(Not measued separately)
Rs 5mΩ
FPGA_1V8 1.8V
C f
G = 125.07
FPGA_1V8
0A-3.2A
CS = 0V-2.00V
VCC3V3 3.3V
(Not measued separately)
Rs 5mΩ
FPGA_3V3 3.3V
C f
G = 125.07
FPGA_3V3
0A-3.2A
CS = 0V-2.00V
Rs 5mΩ
MGTAVCC 1.0V
C f
G = 134.3
MGTAVCC
0A-3.0A
CS = 0V-2.02V
Rs 5mΩ
MGTAVTT 1.2V
C f
G = 268.4
MGTAVTT
0A-1.5A
CS = 0V-2.02V
UG952_c1_138_011513
65