Revision History - Xilinx AC701 User Manual

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Revision History

The following table shows the revision history for this document.
Date Version
10/23/2012 1.0
01/30/2013 1.1
08/28/2013 1.2
AC701 Evaluation Board
Initial Xilinx release.
Updated photograph in Figure 1-2, page 8
Figure 1-3. Revised last paragraph under
paragraph under USB JTAG Module, page
page 26, first paragraph under
third paragraphs under FMC HPC GBT Clocks, page
Express Edge Connector, page
page 36. Revised third and fourth rows in
Table 1-14, page 37. Revised second paragraph and added fourth paragraph under
Character Display, page 45. Revised first paragraph under
Added Figure 1-31, page 51,
Figure 1-40, page 56. Added section
XADC Power System Measurement, page
Management, page 69. Revised
Updated the Master Constraints File Listing in Appendix
Regulatory and Compliance
Added Figure 1-10. Revised
Table 1-18, and Table 1-26. Updated
Appendix C, Master Constraints File
www.xilinx.com
Revision
to revision 1.0 of the AC701 board. Revised
DDR3 Memory Module, page
19, third paragraph under
125 MHz Clock Generator, page
29, fourth paragraph under
34, and the first paragraph under
Table 1-13, page 37
Figure 1-33, page 51 and Figure 1-34, page
AC701 Board Power System, page 61
66. Added third paragraph under
Figure 1-48, page 77. Revised
Information.
Figure 1-2, Figure 1-48, and
Monitoring Voltage and
Listing.
12, fourth
GTP Clock MUX,
27, first, second and
PCI
SFP/SFP+ Connector,
and the fifth row in
I2C Bus Switch, page 47.
52. Revised
and section
Power
Figure A-2, page 80.
C. Added Appendix G,
Figure 1-49. Updated Table
Current. Updated
UG952 (v1.2) August 28, 2013
LCD
1-1,