Xilinx AC701 User Manual page 26

Chapter 1: AC701 Evaluation Board Features
GTP Clock MUX
The AC701 board FPGA U1 MGT Bank 213 has two clock inputs, MGTREFCLK0 and
MGTREFCLK1. Each clock input is driven by a capacitively-coupled clock sourced from a
SY9544UMG 4-to-1 MUX.
Each MUX has a clock source at three of its four inputs, the fourth input is not connected.
Clock MUX U3 SY89544UMG drives Bank 213 MGTREFCLK0 pins AA13 (P) and AB13
(N), and clock MUX U4 SY89544UMG drives Bank 213 MGTREFCLK1 pins AA11 (P) and
AB11 (N). See
connections.
Table 1-9
Table 1-9: MGT Clock MUX U3 and U4 Clock Sources
26
Table 1-10 for clock MUX U3 connections, and
lists the MGT sources for U3 and U4.
Clock Name Reference
125 MHz Clock
Generator
GTP SMA REF Clock
(differential pair)
Jitter Attenuated
Clock
FMC HPC GBT
Clocks
www.xilinx.com
ICS844021 Crystal-to-LVDS Clock Generator (ICS).
U2
See 125 MHz Clock Generator, page
SMA_MGT_REFCLK_P (net name).
J25
See GTP SMA Clock Input, page
SMA_MGT_REFCLK_N (net name).
J26
See GTP SMA Clock Input, page
Si5324C LVDS precision clock multiplier/jitter
attenuator (Silicon Labs).
U24
See Jitter Attenuated Clock, page
FMC_HPC_GBTCLK0_M2C_C_P/N (net name) (U3),
FMC_HPC_GBTCLK1_M2C_C_P/N (net name) (U4).
J30
See FMC HPC GBT Clocks, page
Table 1-11 for clock MUX U4
Description
27.
27.
27.
28.
29.
AC701 Evaluation Board
UG952 (v1.2) August 28, 2013