Xilinx AC701 User Manual page 73

In this VCCO_VADJ off mode, the user can control when to turn on VCCO_VADJ and to
what voltage level (1.8V, 2.5V or 3.3V).
With VCCO_VADJ off, the FPGA still configures and has access to the TI controller PMBus
and the VADJ_ON_B signal which are wired to FPGA U1 Bank 14. The combination of
these features allows the user to develop code to command the VCCO_VADJ rail to be set
to 1.8V or 3.3V instead of the default setting of 2.5V.
Refer to AC701 board schematic page 46 for a brief discussion concerning selectable
VCCO_VADJ voltages. The important controller-to-regulator circuit signals are
VCCO_VADJ_EN and FMC_ADJ_SEL[1:0]. In the VCCO_VADJ off mode, controller U9
does not toggle the regulator turn-on signal VCCO_VADJ_EN high so the U56 regulator
stays off. The user must re-program the controller U9 VCCO_VADJ rail settings to the
desired VCCO_VADJ voltage so that the controller expects the new voltage to appear on its
MON1 remote sense pin. The FMC_ADJ_SEL[1:0] controller GPIO16 and GPIO17 pins
must be set to the correct logic levels to force the VCCO_VADJ regulator Rset MUX U64 to
select the appropriate RT_CLK and VADJ resistors for the desired voltage as shown in
Table
Table 1-34: VCCO_VADJ Voltage Selection
When the new VCCO_VADJ rail settings and Rset MUX logic levels are programmed into
controller U9, the FMC_VADJ_ON_B signal can be driven low by user FPGA logic and the
controller toggles the VCCO_VADJ_EN signal high to allow the rail to come up at the new
VCCO_VADJ voltage level.
Documentation describing PMBus programming for the UCD90120A controller is
available at www.ti.com/fusiondocs.
Cooling Fan Control
Cooling fan RPM is controlled and monitored by user-created IP in the FPGA using the fan
control circuit is shown in
FPGA U1 can be cooled by a user-supplied 12V DC fan connected to J61. 12V
provided to the fan through J61 pin 2. The fan GND return is provided through J61 pin 1
and transistor Q17. Fan speed is controlled by a pulse-width-modulated signal from FPGA
U1 pin J26 (on Bank 15) driving the gate of Q17. The default unprogrammed FPGA fan
operation mode is ON. The fan speed tachometer signal on J61 pin 3 can be monitored on
FPGA U1 pin J25 (on Bank 15).
AC701 Evaluation Board
UG952 (v1.2) August 28, 2013
1-34.
FMC_ADJ_SEL[10]
BIT 1 BIT 0
0
0
1
1
Figure
www.xilinx.com
VCCO_ADJ (V)
0 2.5V
1 1.8V
0 3.3V
1 NOT USED
1-45.
Feature Descriptions
is
DC
73