Xilinx AC701 User Manual page 94

Appendix C: Master Constraints File Listing
94
#XADC
set_property PACKAGE_PIN H17 [get_ports XADC_GPIO_0]
set_property IOSTANDARD LVCMOS25 [get_ports XADC_GPIO_0]
set_property PACKAGE_PIN E22 [get_ports XADC_GPIO_1]
set_property IOSTANDARD LVCMOS25 [get_ports XADC_GPIO_1]
set_property PACKAGE_PIN K18 [get_ports XADC_GPIO_2]
set_property IOSTANDARD LVCMOS25 [get_ports XADC_GPIO_2]
set_property PACKAGE_PIN L19 [get_ports XADC_GPIO_3]
set_property IOSTANDARD LVCMOS25 [get_ports XADC_GPIO_3]
set_property PACKAGE_PIN K15 [get_ports XADC_VAUX0_R_P]
set_property IOSTANDARD LVCMOS25 [get_ports XADC_VAUX0_R_P]
set_property PACKAGE_PIN J16 [get_ports XADC_VAUX0_R_N]
set_property IOSTANDARD LVCMOS25 [get_ports XADC_VAUX0_R_N]
set_property PACKAGE_PIN J14 [get_ports XADC_VAUX8_R_P]
set_property IOSTANDARD LVCMOS25 [get_ports XADC_VAUX8_R_P]
set_property PACKAGE_PIN J15 [get_ports XADC_VAUX8_R_N]
set_property IOSTANDARD LVCMOS25 [get_ports XADC_VAUX8_R_N]
set_property PACKAGE_PIN K16 [get_ports XADC_AD1_R_P]
set_property IOSTANDARD LVCMOS25 [get_ports XADC_AD1_R_P]
set_property PACKAGE_PIN K17 [get_ports XADC_AD1_R_N]
set_property IOSTANDARD LVCMOS25 [get_ports XADC_AD1_R_N]
set_property PACKAGE_PIN M15 [get_ports XADC_AD9_R_P]
set_property IOSTANDARD LVCMOS25 [get_ports XADC_AD9_R_P]
set_property PACKAGE_PIN L15 [get_ports XADC_AD9_R_N]
set_property IOSTANDARD LVCMOS25 [get_ports XADC_AD9_R_N]
set_property PACKAGE_PIN B25 [get_ports XADC_MUX_ADDR0_LS]
set_property IOSTANDARD LVCMOS25 [get_ports XADC_MUX_ADDR0_LS]
set_property PACKAGE_PIN A25 [get_ports XADC_MUX_ADDR1_LS]
set_property IOSTANDARD LVCMOS25 [get_ports XADC_MUX_ADDR1_LS]
set_property PACKAGE_PIN A23 [get_ports XADC_MUX_ADDR2_LS]
set_property IOSTANDARD LVCMOS25 [get_ports XADC_MUX_ADDR2_LS]
#IIC
set_property PACKAGE_PIN R17 [get_ports IIC_MUX_RESET_B]
set_property IOSTANDARD LVCMOS33 [get_ports IIC_MUX_RESET_B]
set_property PACKAGE_PIN N18 [get_ports IIC_SCL_MAIN]
set_property IOSTANDARD LVCMOS33 [get_ports IIC_SCL_MAIN]
set_property PACKAGE_PIN K25 [get_ports IIC_SDA_MAIN]
set_property IOSTANDARD LVCMOS33 [get_ports IIC_SDA_MAIN]
#DDR3
set_property PACKAGE_PIN N8 [get_ports DDR3_RESET_B]
set_property IOSTANDARD LVCMOS15 [get_ports DDR3_RESET_B]
set_property PACKAGE_PIN M2 [get_ports DDR3_CLK0_P]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_CLK0_P]
set_property PACKAGE_PIN L2 [get_ports DDR3_CLK0_N]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_CLK0_N]
set_property PACKAGE_PIN N3 [get_ports DDR3_CLK1_P]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_CLK1_P]
set_property PACKAGE_PIN N2 [get_ports DDR3_CLK1_N]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_CLK1_N]
set_property PACKAGE_PIN P4 [get_ports DDR3_CKE0]
set_property IOSTANDARD SSTL15 [get_ports DDR3_CKE0]
set_property PACKAGE_PIN N4 [get_ports DDR3_CKE1]
set_property IOSTANDARD SSTL15 [get_ports DDR3_CKE1]
set_property PACKAGE_PIN R1 [get_ports DDR3_WE_B]
set_property IOSTANDARD SSTL15 [get_ports DDR3_WE_B]
set_property PACKAGE_PIN P1 [get_ports DDR3_RAS_B]
set_property IOSTANDARD SSTL15 [get_ports DDR3_RAS_B]
set_property PACKAGE_PIN T4 [get_ports DDR3_CAS_B]
set_property IOSTANDARD SSTL15 [get_ports DDR3_CAS_B]
set_property PACKAGE_PIN T3 [get_ports DDR3_S0_B]
set_property IOSTANDARD SSTL15 [get_ports DDR3_S0_B]
set_property PACKAGE_PIN T2 [get_ports DDR3_S1_B]
www.xilinx.com AC701 Evaluation Board
UG952 (v1.2) August 28, 2013