Xilinx AC701 User Manual page 27

125 MHz Clock Generator
[Figure
Clock MUX U3 input 0 (pin4 P, pin 2 N) is driven by U2 ICS84402I Crystal-to-LVDS clock
generator. This device uses 25 MHz crystal X3 as its base input frequency and, via an
internal VCO, multiplies this by five to produce a 0.45 ps (typical) RMS phase jitter,
125 MHz LVDS output. The circuit for the 125 MHz clock is shown in
X-Ref Target - Figure 1-14
C300
18pF 50V
NPO
X3
R320 2
GND1
1.0M 5%
4
GND2
C301
18pF 50V
NPO
GND_EPHYCLK GND_EPHYCLK
Figure 1-14: AC701 Board 125 MHz U3 MUX Input0 Source Circuit
GTP SMA Clock Input
[Figure
The AC701 board includes a pair of SMA connectors for a GTP clock that are wired to GTP
quad bank 213 via clock MUX U4. This differential clock has signal names
SMA_MGT_REFCLK_P and SMA_REFCLK_N, which are connected to MGT clock MUX
U4 input 0 pins 4 and 2 respectively. The clock MUX output pins 10 (P-side) and 11 (N-side)
are capacitively coupled to FPGA U1 GTP quad 213 MGTREFCLK1 pin AA11 and AB11
respectively.
•
•
X-Ref Target - Figure 1-15
AC701 Evaluation Board
UG952 (v1.2) August 28, 2013
1-2, callout 15]
VDDA_EPHYCLK
25.00 MHz
50 ppm
EPHYCLK_XTAL_OUT
X1 1
EPHYCLK_XTAL_IN
3
X2
GND_EPHYCLK
1-2, callout 9]
Figure 1-15 shows this direct-coupled SMA clock input circuit.
External user-provided GTP reference clock on SMA input connectors
Differential Input
J25
SMA
Connector
J26
SMA
Connector
Figure 1-15: GTP SMA Clock Source
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VDD_EPHYCLK
U2
ICS844021I
1 8
VDDA VDD
2 7
GND Q0
3 6
XTAL_OUT NQ0
4 5
XTAL_IN OE
SMA_MGT_REFCLK_C_P
GND
SMA_MGT_REFCLK_C_N
GND
Feature Descriptions
Figure 1-14.
R486
0Ω 5%
EPHYCLK_Q0_C_P EPHYCLK_Q0_P
EPHYCLK_Q0_C_N EPHYCLK_Q0_N
R487
0Ω 5%
UG952_c1_13_101512
R485
SMA_MGT_REFCLK_P
0Ω 5%
R484
SMA_MGT_REFCLK_N
0Ω 5%
UG952_c1_14_101512
27