Xilinx AC701 User Manual page 25

User SMA Clock Input
[Figure
An external high-precision clock signal can be provided to the FPGA bank 15 by
connecting differential clock signals through the onboard 50Ω SMA connectors J31 (P) and
J32 (N). The differential clock signal names are USER_SMA_CLOCK_P and
USER_SMA_CLOCK_N, which are connected to FPGA U1 pins J23 and H23 respectively.
The user-provided differential clock circuit is shown in
Note:
VCCO_VADJ rail is typically 2.5V but can be reprogrammed to be either 1.8V or 3.3V. The
USER_SMA_CLOCK_P/N signals should not exceed the VCCO_VADJ voltage (1.8V, 2.5V or 3.3V)
in use.
X-Ref Target - Figure 1-13
AC701 Evaluation Board
UG952 (v1.2) August 28, 2013
1-2, callout 8]
This user clock is input to FPGA bank 15 which is powered by VCCO_VADJ. The
SMA
Connector
SMA
Connector
Figure 1-13: User SMA Clock Source
www.xilinx.com
Figure
J31
USER_SMA_CLOCK_P
J32 GND
USER_SMA_CLOCK_N
GND
UG952_c1_12_100212
Feature Descriptions
1-13.
25