Xilinx AC701 User Manual page 86

Appendix C: Master Constraints File Listing
86
set_property IOSTANDARD LVCMOS33 [get_ports SDIO_DAT1]
set_property PACKAGE_PIN P23 [get_ports SDIO_DAT2]
set_property IOSTANDARD LVCMOS33 [get_ports SDIO_DAT2]
set_property PACKAGE_PIN P21 [get_ports SDIO_CD_DAT3]
set_property IOSTANDARD LVCMOS33 [get_ports SDIO_CD_DAT3]
#PMBUS
set_property PACKAGE_PIN R21 [get_ports PMBUS_CLK_LS]
set_property IOSTANDARD LVCMOS33 [get_ports PMBUS_CLK_LS]
set_property PACKAGE_PIN R25 [get_ports PMBUS_DATA_LS]
set_property IOSTANDARD LVCMOS33 [get_ports PMBUS_DATA_LS]
set_property PACKAGE_PIN P25 [get_ports PMBUS_CTRL_LS]
set_property IOSTANDARD LVCMOS33 [get_ports PMBUS_CTRL_LS]
set_property PACKAGE_PIN N26 [get_ports PMBUS_ALERT_LS]
set_property IOSTANDARD LVCMOS33 [get_ports PMBUS_ALERT_LS]
set_property PACKAGE_PIN P26 [get_ports PMOD_0]
set_property IOSTANDARD LVCMOS33 [get_ports PMOD_0]
set_property PACKAGE_PIN T22 [get_ports PMOD_1]
set_property IOSTANDARD LVCMOS33 [get_ports PMOD_1]
set_property PACKAGE_PIN R22 [get_ports PMOD_2]
set_property IOSTANDARD LVCMOS33 [get_ports PMOD_2]
set_property PACKAGE_PIN T23 [get_ports PMOD_3]
set_property IOSTANDARD LVCMOS33 [get_ports PMOD_3]
#SFP
set_property PACKAGE_PIN B26 [get_ports SFP_MGT_CLK_SEL0]
set_property IOSTANDARD LVCMOS25 [get_ports SFP_MGT_CLK_SEL0]
set_property PACKAGE_PIN C24 [get_ports SFP_MGT_CLK_SEL1]
set_property IOSTANDARD LVCMOS25 [get_ports SFP_MGT_CLK_SEL1]
set_property PACKAGE_PIN R23 [get_ports SFP_LOS]
set_property IOSTANDARD LVCMOS33 [get_ports SFP_LOS]
set_property PACKAGE_PIN R18 [get_ports SFP_TX_DISABLE]
set_property IOSTANDARD LVCMOS33 [get_ports SFP_TX_DISABLE]
#PCI-E
set_property PACKAGE_PIN A24 [get_ports PCIE_MGT_CLK_SEL0]
set_property IOSTANDARD LVCMOS25 [get_ports PCIE_MGT_CLK_SEL0]
set_property PACKAGE_PIN C26 [get_ports PCIE_MGT_CLK_SEL1]
set_property IOSTANDARD LVCMOS25 [get_ports PCIE_MGT_CLK_SEL1]
set_property PACKAGE_PIN K26 [get_ports PCIE_WAKE_B]
set_property IOSTANDARD LVCMOS33 [get_ports PCIE_WAKE_B]
set_property PACKAGE_PIN M20 [get_ports PCIE_PERST]
set_property IOSTANDARD LVCMOS33 [get_ports PCIE_PERST]
#USR CLOCKS
set_property PACKAGE_PIN M19 [get_ports SI5324_INT_ALM_B]
set_property IOSTANDARD LVCMOS33 [get_ports SI5324_INT_ALM_B]
set_property PACKAGE_PIN B24 [get_ports SI5324_RST_LS_B]
set_property IOSTANDARD LVCMOS25 [get_ports SI5324_RST_LS_B]
set_property PACKAGE_PIN D23 [get_ports REC_CLOCK_C_P]
set_property IOSTANDARD LVDS_25 [get_ports REC_CLOCK_C_P]
set_property PACKAGE_PIN D24 [get_ports REC_CLOCK_C_N]
set_property IOSTANDARD LVDS_25 [get_ports REC_CLOCK_C_N]
set_property PACKAGE_PIN R3 [get_ports SYSCLK_P]
set_property IOSTANDARD LVDS_25 [get_ports SYSCLK_P]
set_property PACKAGE_PIN P3 [get_ports SYSCLK_N]
set_property IOSTANDARD LVDS_25 [get_ports SYSCLK_N]
#MGTs
set_property PACKAGE_PIN AB13 [get_ports SFP_MGT_CLK0_N]
set_property IOSTANDARD LVDS_25 [get_ports SFP_MGT_CLK0_N]
set_property PACKAGE_PIN AA13 [get_ports SFP_MGT_CLK0_P]
set_property IOSTANDARD LVDS_25 [get_ports SFP_MGT_CLK0_P]
set_property PACKAGE_PIN AA11 [get_ports SFP_MGT_CLK1_P]
set_property IOSTANDARD LVDS_25 [get_ports SFP_MGT_CLK1_P]
www.xilinx.com AC701 Evaluation Board
UG952 (v1.2) August 28, 2013