Xilinx AC701 User Manual page 29

FMC HPC GBT Clocks
The FMC HPC connector J30 sources two MGT clocks, FMC1_HPC_GBTCLK0_M2C_P/N
from connector section D, and FMC1_HPC_GBTCLK1_M2C_P/N from connector
section B.
Table 1-10: MUX U3 SY89544UMG MGT Clock Inputs
Clock Source
Ref
Device Pin
Des
7
ICS84402I U2
6
29
SI5324-C-GM U24
28
D4
FMC HPC J30
D5
Notes:
1. U3 output clock nets SFP_MGT_CLK0_P/N contain a series 0.1uF capacitor.
The MUX U3 clock input channel select nets are SFP_MGT_CLK_SEL[1:0].
SFP_MGT_CLK_SEL1 is wired to FPGA U1 pin C24 and SFP_MGT_CLK_SEL0 is wired to
FPGA U1 pin B26 on FPGA U1 Bank 16.
Table 1-11: MUX U4 SY89544UMG MGT Clock Inputs
Clock Source
Ref
Device Pin
Des
SMA J25 1
SMA J26 1
35
SI5324-C-GM U24
34
B20
FMC HPC J30
B21
Notes:
1. U4 output clock nets SFP_MGT_CLK1_P/N contain a series 0.1uF capacitor.
The MUX U4 clock input channel select nets are PCIE_MGT_CLK_SEL[1:0].
PCIE_MGT_CLK_SEL1 is wired to FPGA U1 pin C26 and PCIE_MGT_CLK_SEL0 is wired
to FPGA U1 pin A24 on FPGA U1 Bank 16.
The U3 MUX circuit is shown in
AC701 Evaluation Board
UG952 (v1.2) August 28, 2013
Table 1-10 and Table 1-11
Schematic Net Name
Input Pin Output Pin
EPHYCLK_Q0_P
IN0
EPHYCLK_Q0_N
SI5324_OUT0_C_N
IN1
SI5324_OUT0_C_P
FMC1_HPC_
GBTCLK0_M2C_P
IN2
FMC1_HPC_
GBTCLK0_M2C_N
Schematic Net Name
Input Pin Output Pin
SMA_MGT_REFCLK_P
IN0
SMA_MGT_REFCLK_N
SI5324_OUT1_C_P
IN1
SI5324_OUT1_C_N
FMC1_HPC_
GBTCLK1_M2C_P
IN2
FMC1_HPC_
GBTCLK1_M2C_N
www.xilinx.com
list the MGT clock MUX U3 and U4 connections.
SY89544UMG U3
Schematic Net Name
4
2
32
Qout_P 10 SFP_MGT_CLK0_P
30
Qout_N 11 SFP_MGT_CLK0_N
27
25
SY89544UMG U4 Schematic Net Name
4
2
32
Qout_P 10 SFP_MGT_CLK1_P
30
Qout_N 11 SFP_MGT_CLK1_N
27
25
Figure 1-17. The U4 MUX circuit is shown in
Feature Descriptions
FPGA U1 Bank 213
Pin Pin Name
(1)
AA13 MGTREFCLK0P
(1)
AB13 MGTREFCLK0N
FPGA U1 Bank 213
Pin Pin Name
(1)
AA11 MGTREFCLK1P
(1)
AB11 MGTREFCLK1N
Figure 1-18.
29