Xilinx AC701 User Manual page 63

Figure 1-41
X-Ref Target - Figure 1-41
U8
UCD90120A
Controller
(Controller 1)
Rail Enable
GPIO (Out)
PWM Margin
FPWM (Out)
Current Sense
ADC (In)
Voltage Sense
ADC (In)
Low Pwr Select
GPIO (Out)
Rail Enable
GPIO (Out)
PWM Margin
FPWM (Out)
Current Sense
ADC (In)
Voltage Sense
ADC (In)
Rail Enable
GPIO (Out)
PWM Margin
FPWM (Out)
Current Sense
ADC (In)
Voltage Sense
ADC (In)
Rail Enable
GPIO (Out)
PWM Margin
FPWM (Out)
Current Sense
ADC (In)
Voltage Sense
ADC (In)
Notes:
1. Capacitors labled C f are bulk filter capacitors.
2. Voltage Sense is connected at point of load.
AC701 Evaluation Board
UG952 (v1.2) August 28, 2013
shows the power system for UCD90120A U8 controller #1
+12V
(2)
+12V
(2)
+12V
(2)
+12V
(2)
Figure 1-41: U8 Controller #1 UCD90120A Power System
www.xilinx.com
U49 (1.0V Nom)
LMZ12008
Vin Vout
Input
C f
Filter
EN
V
fb
FB
U53 (1.8V Nom)
TPS84621
Vin Vout
Input
C f
Filter
EN
V
fb
FB
U54 (1.0V Nom)
TPS84320
Vin Vout
Input
C f
Filter
EN
V
fb
FB
U55 (1.5V Nom)
TPS84621
Vin Vout
Input
C f
Filter
EN
V
fb
FB
Feature Descriptions
Rs 5mΩ
VCCINT 1.0V
(1)
C f
G = 40.22
VCCINT 0A-10A
CS = 0V-2.01V
Rs 5mΩ
VCCAUX 1.8V
C f
G = 67.67
VCCAUX 0A-6A
CS = 0V-2.03V
Rs 5mΩ
VCCBRAM 1.0V
C f
G = 221.7
VCCVBRAM
0A-1.8A
CS = 0V-1.996V
Rs 5mΩ
FPGA_1V5 1.5V
C f
G = 67.67
FPGA_1V5
0A- 6A
CS = 0V-2.03V
UG952_c1_137_011513
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