Xilinx AC701 User Manual page 35

The PCIe clock is input from the edge connector. It is AC coupled to the FPGA through the
MGTREFCLK0 pins of Quad 216. PCIE_CLK_Q0_P is connected to FPGA U1 pin F11, and
the _N net is connected to pin E11. The PCI Express clock circuit is shown in
X-Ref Target - Figure 1-19
PCIe lane width/size is selected via jumper J12
selection is 4-lane (J12 pins 3 and 4) jumpered).
X-Ref Target - Figure 1-20
Table 1-12, page 33
For more information refer to UG476, 7 Series FPGAs GTP Transceivers User Guide and
UG477
AC701 Evaluation Board
UG952 (v1.2) August 28, 2013
P1
PCI Express
Four-Lane
Edge connector
OE
A12
GND
A13
REFCLK+
A14
REFCLK-
A15
GND
Figure 1-19: PCI Express Clock
PCIE_PRSNT_X1
PCIE_PRSNT_X4
Figure 1-20: PCI Express Lane Size Select Jumper J12
lists the PCIe edge connector connections.
7 Series FPGAs Integrated Block for PCI Express User Guide (AXI).
www.xilinx.com
C188
0.01µF 25V
X7R
PCIE_CLK_Q0_C_P PCIE_CLK_Q0_P
PCIE_CLK_Q0_C_N PCIE_CLK_Q0_N
C189
0.01µF 25V
X7R
GND
(Figure 1-20). The default lane size
J12
PCIE_PRSNT_B
1 2
3 4
UG952_c1_19_100312
Feature Descriptions
Figure 1-19.
UG952_c1_18_100312
35