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Xilinx AC701 User Manual

Evaluation board for the artix-7 fpga
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AC701 Evaluation Board
for the Artix-7 FPGA
User Guide
UG952 (v1.2) August 28, 2013

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Summary of Contents for Xilinx AC701

  • Page 1 AC701 Evaluation Board for the Artix-7 FPGA User Guide UG952 (v1.2) August 28, 2013...

  • Page 2: Revision History

    Limited Warranties which can be viewed at http://www.xilinx.com/warranty.htm; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance;...

  • Page 3: Table Of Contents

    AC701 Board Power System ........
  • Page 4 Appendix D: Board Setup Installing the AC701 Board in a PC Chassis ........99...

  • Page 5: Chapter 1: Ac701 Evaluation Board Features

    Chapter 1 AC701 Evaluation Board Features Overview The AC701 evaluation board for the Artix®-7 FPGA provides a hardware environment for developing and evaluating designs targeting the Artix-7 XC7A200T-2FBG676C FPGA. The AC701 board provides features common to many embedded processing systems, including a DDR3 SODIMM memory, an 4-lane PCI Express®...
  • Page 6 Chapter 1: AC701 Evaluation Board Features • Gen1 4-lane (x4) • Gen2 4-lane (x4) • SFP+ Connector • 10/100/1000 tri-speed Ethernet PHY • USB-to-UART bridge • High-Definition Multimedia Interface (HDMI™) codec • C bus • C MUX • C EEPROM (1 KB) •...
  • Page 7 AC701 Evaluation Kit product page. Caution! The AC701 board can be damaged by electrostatic discharge (ESD). Follow standard ESD prevention measures when handling the board X-Ref Target - Figure 1-1 1 GB DDR3 Memory...

  • Page 8: Feature Descriptions

    Chapter 1: AC701 Evaluation Board Features Feature Descriptions Figure 1-2 shows the AC701 board. Each numbered feature that is referenced in Figure 1-2 is described in the sections that follow. Note: Figure 1-2 The image in is for reference only and might not reflect the current revision of the board.

  • Page 9: Artix-7 Fpga

    For further information on Artix-7 FPGAs, see DS180 , 7 Series FPGAs Overview FPGA Configuration The AC701 board supports two of the five 7 series FPGA configuration modes: • Master SPI using the on-board Quad SPI Flash memory • JTAG using a standard-A to micro-B USB cable for connecting the host PC to the...
  • Page 10 For full details on configuring the FPGA, see UG470, 7 Series FPGAs Configuration User Guide Encryption Key Backup Circuit FPGA U1 implements bitstream encryption key technology. The AC701 board provides the encryption key backup battery circuit shown in Figure 1-4. The rechargeable 1.5V lithium button-type battery B1 is soldered to the board with the positive output connected to FPGA U1 VCCBATT pin G14.
  • Page 11 Figure 1-4: Encryption Key Backup Circuit I/O Voltage Rails In addition to Bank 0, there are 8 I/O banks available on the Artix-7 device. The voltages applied to the FPGA I/O banks used by the AC701 board are listed in Table 1-3.

  • Page 12: Ddr3 Memory Module

    Chapter 1: AC701 Evaluation Board Features DDR3 Memory Module [Figure 1-2, callout 2] The memory module at J1 is a 1 GB DDR3 small outline dual-inline memory module (SODIMM). It provides volatile synchronous dynamic random access memory (SDRAM) for storing user code and data. The SODIMM socket has a perforated EMI shield...
  • Page 13 DQ17 DDR3_D18 DQ18 DDR3_D19 DQ19 DDR3_D20 DQ20 DDR3_D21 DQ21 DDR3_D22 DQ22 DDR3_D23 DQ23 DDR3_D24 DQ24 DDR3_D25 DQ25 DDR3_D26 DQ26 DDR3_D27 DQ27 DDR3_D28 DQ28 DDR3_D29 DQ29 DDR3_D30 DQ30 DDR3_D31 DQ31 DDR3_D32 DQ32 AC701 Evaluation Board www.xilinx.com UG952 (v1.2) August 28, 2013...
  • Page 14 Chapter 1: AC701 Evaluation Board Features Table 1-4: DDR3 Memory Connections to the FPGA (Cont’d) J1 DDR3 Memory U1 FPGA Pin Net Name Pin Number Pin Name DDR3_D33 DQ33 DDR3_D34 DQ34 DDR3_D35 DQ35 DDR3_D36 DQ36 DDR3_D37 DQ37 DDR3_D38 DQ38 DDR3_D39...
  • Page 15 DDR3_DQS4_P DQS4_P DDR3_DQS5_N DQS5_N DDR3_DQS5_P DQS5_P DDR3_DQS6_N DQS6_N DDR3_DQS6_P DQS6_P DDR3_DQS7_N DQS7_N DDR3_DQS7_P DQS7_P DDR3_ODT0 ODT0 DDR3_ODT1 ODT1 DDR3_RESET_B RESET_B DDR3_S0_B S0_B DDR3_S1_B S1_B DDR3_TEMP_ EVENT_B EVENT DDR3_WE_B WE_B DDR3_CAS_B CAS_B AC701 Evaluation Board www.xilinx.com UG952 (v1.2) August 28, 2013...

  • Page 16: Quad-Spi Flash Memory

    The AC701 board DDR3 memory interface adheres to the constraints guidelines documented in the DDR3 Design Guidelines section of UG586, 7 Series FPGAs Memory Interface Solutions User Guide. The AC701 board DDR3 memory interface is a 40Ω impedance implementation. Other memory interface details are available in...

  • Page 17: Spi External Programming Header

    The configuration section of UG470, 7 Series FPGAs Configuration User Guide provides details on using the Quad-SPI Flash memory. Figure 1-5 shows the connections of the Quad-SPI Flash memory on the AC701 board. For more details, see the Micron N25Q256A13ESF40G data sheet [Ref X-Ref Target - Figure 1-5...

  • Page 18: Sd Card Interface

    [Figure 1-2, callout 4] The AC701 board includes a secure digital input/output (SDIO) interface to provide user-logic access to general purpose non-volatile SDIO memory cards and peripherals. The SD card slot is designed to support 50 MHz high speed SD cards.

  • Page 19: Usb Jtag Module

    (host side) to micro-B plug (AC701 board side) USB cable. A 2-mm JTAG header (J4) is also provided in parallel for access by Xilinx download cables such as the Platform Cable USB II and the Parallel Cable IV.
  • Page 20 Chapter 1: AC701 Evaluation Board Features When an FMC daughter card is attached to the AC701 board it is automatically added to the JTAG chain through electronically controlled single-pole single-throw (SPST) switches U27. The SPST switch is in a normally closed state and transitions to an open state when an FMC daughter card is attached.

  • Page 21: Clock Generation

    Feature Descriptions Clock Generation There are three clock sources available for the FPGA logic on the AC701 board (refer to Table 1-8). Table 1-8: AC701 Board Clock Sources Clock Name Reference Description System Clock SiT9102 2.5V LVDS 200 MHz Fixed Frequency Oscillator (Si Time).
  • Page 22 Chapter 1: AC701 Evaluation Board Features X-Ref Target - Figure 1-10 Figure 1-10: AC701 Clocking Diagram www.xilinx.com AC701 Evaluation Board UG952 (v1.2) August 28, 2013...
  • Page 23 [Figure 1-2, callout 6] The AC701 board has a 2.5V LVDS differential 200 MHz oscillator (U51) soldered onto the back side of the board and wired to an FPGA MRCC clock input on bank 34. This 200 MHz signal pair is named SYSCLK_P and SYSCLK_N, which are connected to FPGA U1 pins R3 and P3 respectively.
  • Page 24 156.250 MHz. User applications can change the output frequency within the range of 10 MHz to 810 MHz through an I C interface. Power cycling the AC701 board will revert the user clock to its default frequency of 156.250 MHz. •...
  • Page 25 VCCO_VADJ rail is typically 2.5V but can be reprogrammed to be either 1.8V or 3.3V. The USER_SMA_CLOCK_P/N signals should not exceed the VCCO_VADJ voltage (1.8V, 2.5V or 3.3V) in use. X-Ref Target - Figure 1-13 USER_SMA_CLOCK_P Connector USER_SMA_CLOCK_N Connector UG952_c1_12_100212 Figure 1-13: User SMA Clock Source AC701 Evaluation Board www.xilinx.com UG952 (v1.2) August 28, 2013...
  • Page 26 Chapter 1: AC701 Evaluation Board Features GTP Clock MUX The AC701 board FPGA U1 MGT Bank 213 has two clock inputs, MGTREFCLK0 and MGTREFCLK1. Each clock input is driven by a capacitively-coupled clock sourced from a SY9544UMG 4-to-1 MUX. Each MUX has a clock source at three of its four inputs, the fourth input is not connected.
  • Page 27 [Figure 1-2, callout 9] The AC701 board includes a pair of SMA connectors for a GTP clock that are wired to GTP quad bank 213 via clock MUX U4. This differential clock has signal names SMA_MGT_REFCLK_P and SMA_REFCLK_N, which are connected to MGT clock MUX U4 input 0 pins 4 and 2 respectively.
  • Page 28 [Figure 1-2, callout 10] The AC701 board includes a Silicon Labs Si5324 jitter attenuator U24 on the back side of the board. FPGA user logic can implement a clock recovery circuit and then output this clock to a differential I/O pair on I/O bank 16 (REC_CLOCK_C_P, FPGA U1 pin D23 and REC_CLOCK_C_N, FPGA U1 pin D24) for jitter attenuation.
  • Page 29 PCIE_MGT_CLK_SEL1 is wired to FPGA U1 pin C26 and PCIE_MGT_CLK_SEL0 is wired to FPGA U1 pin A24 on FPGA U1 Bank 16. The U3 MUX circuit is shown in Figure 1-17. The U4 MUX circuit is shown in Figure 1-18. AC701 Evaluation Board www.xilinx.com UG952 (v1.2) August 28, 2013...
  • Page 30 Chapter 1: AC701 Evaluation Board Features X-Ref Target - Figure 1-17 VCC2V5 VCC2V5 SY89544UMG C105 VCC1 VCC3 0.1µF VCC2 VCC4 EPHYCLK_Q0_P VCC5 VCC6 C320 EPHYCLK_Q0_N VCC7 0.1µF SI5324_OUT0_C_P VCC8 SFP_MGT_CLK0_P SI5324_OUT0_C_N SFP_MGT_CLK0_P FMC1_HBC_GBTCLK0_M2C_C_P C318 TO MGT BANK 213 GND1 0.1µF...
  • Page 31 SEL0 PWRPAD SEL1 MGT_CLK1_SEL1 MGT_CLK1_SEL0 VCC2V5 R452 1/10W NDS336P PCIE_MGT_CLK_SEL0 460 mW R151 1/10W VCC2V5 R453 1/10W NDS336P PCIE_MGT_CLK_SEL1 460 mW R152 1/10W UG952_c1_17_101612 Figure 1-18: MGT Clock MUX U4 Circuit AC701 Evaluation Board www.xilinx.com UG952 (v1.2) August 28, 2013...

  • Page 32: Gtp Transceivers

    The GTP transceivers in 7 series FPGAs are grouped into four channels described as Quads. The reference clock for a Quad can be sourced from the Quad above or Quad below the GTP Quad of interest. There are two GTP Quads on the AC701 board with connectivity as shown here: •...
  • Page 33 Clock Input SMA GTPE2_CHANNEL_ AA13 MGTREFCLK0P_213 SFP_MGT_CLK0_C_P U3.10 Clock Mux U3 X0Y0 AB13 MGTREFCLK0N_213 SFP_MGT_CLK0_C_N U3.11 Clock Mux U3 AA11 MGTREFCLK1P_213 SFP_MGT_CLK1_C_P U4.10 Clock Mux U4 AB11 MGTREFCLK1N_213 SFP_MGT_CLK1_C_N U4.11 Clock Mux U4 AC701 Evaluation Board www.xilinx.com UG952 (v1.2) August 28, 2013...

  • Page 34: Pci Express Edge Connector

    85Ω ±10%. The PCIe clock is routed as a 100Ω differential pair. The 7 series FPGAs GTP transceivers are used for multi-gigabit per second serial interfaces. The XC7A200T-2FBG676C FPGA (-2 speed grade) included with the AC701 board supports up to Gen2 x4. www.xilinx.com AC701 Evaluation Board UG952 (v1.2) August 28, 2013...
  • Page 35 PCIe edge connector connections. For more information refer to UG476, 7 Series FPGAs GTP Transceivers User Guide and UG477 7 Series FPGAs Integrated Block for PCI Express User Guide (AXI). AC701 Evaluation Board www.xilinx.com UG952 (v1.2) August 28, 2013...

  • Page 36: Sfp/Sfp+ Connector

    Chapter 1: AC701 Evaluation Board Features SFP/SFP+ Connector [Figure 1-2, callout 13] The AC701 board contains a small form-factor pluggable (SFP+) connector and cage assembly (P3) that accepts SFP or SFP+ modules. Figure 1-21 shows the SFP+ module connector circuitry.
  • Page 37 SFP_RS1 Jumper J39 Jumper Pins 1-2 = Full TX Bandwidth Jumper Pins 2-3 = Reduced TX Bandwidth SFP_LOS Test Point J20 High = Loss of Receiver Signal Low = Normal Operation AC701 Evaluation Board www.xilinx.com UG952 (v1.2) August 28, 2013...

  • Page 38: 10/100/1000 Mb/S Tri-Speed Ethernet Phy

    [Figure 1-2, callout 14] The AC701 board uses the Marvell Alaska PHY device (88E1116R) at U12 for Ethernet communications at 10 Mb/s, 100 Mb/s, or 1,000 Mb/s. The board supports RGMII mode only. The PHY connection to a user-provided ethernet cable is through a Halo HFJ11-1G01E RJ-45 connector (P4) with built-in magnetics.
  • Page 39 Schematic Net Name Name PHY_MDIO MDIO PHY_MDC PHY_TX_CLK TX_CLK PHY_TX_CTRL TX_CTRL PHY_TXD3 TXD3 PHY_TXD2 TXD2 PHY_TXD1 TXD1 PHY_TXD0 TXD0 PHY_RX_CLK RX_CLK PHY_RX_CTRL RX_CTRL PHY_RXD3 RXD3 PHY_RXD2 RXD2 PHY_RXD1 RXD1 PHY_RXD0 RXD0 PHY_RESET_B RESET_B AC701 Evaluation Board www.xilinx.com UG952 (v1.2) August 28, 2013...

  • Page 40: Ethernet Phy User Leds

    Chapter 1: AC701 Evaluation Board Features Ethernet PHY Clock Source A 25.00 MHz, 50 ppm crystal at X1 is the clock source for the 88E1116R PHY at U12. Figure 1-22 shows the clock source. X-Ref Target - Figure 1-22 C406 18pF 50V 25.00 MHz...

  • Page 41: Usb-To-Uart Bridge

    USB cable is plugged into the USB port on the AC701 board. Xilinx UART IP is expected to be implemented in the FPGA logic. The FPGA supports the USB-to-UART bridge using four signal pins: Transmit (TX), Receive (RX), Request to Send (RTS), and Clear to Send (CTS).

  • Page 42: Hdmi Video Output

    [Figure 1-2, callout 17] The AC701 board provides a HDMI video output using the Analog Devices ADV7511KSTZ-P HDMI transmitter (U48). The HDMI output is provided on a Molex 500254-1927 HDMI type-A connector (P2). The ADV7511 is wired to support 1080P 60Hz, YCbCr 4:4:4 encoding via 24-bit input data mapping.
  • Page 43 HDMI_CEC DSD3 DSD4 DSD5 DSD_CLK MCLK GND1 GND2 GND3 I2S0 GND4 I2S1 GND5 I2S2 GND6 I2S3 GND7 SCLK GND8 LRCLK GND9 GND10 R_EXT GND11 R102 UG952_c1_23_100312 Figure 1-24: HDMI Codec Circuit AC701 Evaluation Board www.xilinx.com UG952 (v1.2) August 28, 2013...
  • Page 44 Chapter 1: AC701 Evaluation Board Features Table 1-19 lists the connections between the codec and the FPGA. Table 1-19: FPGA to HDMI Codec Connections (ADV7511) ADV7511 (U48) FPGA Pin (U1) Schematic Net Name Name AA24 HDMI_R_D4 HDMI_R_D5 HDMI_R_D6 HDMI_R_D7 HDMI_R_D8...

  • Page 45: Lcd Character Display

    Information about the ADV7511 is available on the Analog Devices website [Ref LCD Character Display [Figure 1-2, callout 18] A 2-line by 16-character display is provided on the AC701 board (Figure 1-25). X-Ref Target - Figure 1-25 LCD Display (16 x 2)
  • Page 46 UG952_c1_25_100312 Figure 1-26: LCD Interface Circuit The AC701 board base board uses a male Samtec MTLW-107-07-G-D-265 2x7 header (J23) with 0.025-inch square posts on 0.100-inch centers for connecting to a Samtec SLW-107-01-L-D female socket on the LCD display panel assembly. The LCD header...

  • Page 47: I 2 C Bus Switch

    C Bus Switch [Figure 1-2, callout 19] The AC701 board implements a single I C port on FPGA Bank 14 (IIC_SDA_MAIN, FPGA pin K25 and IIC_SCL_MAIN, FPGA pin N18), which is routed through a Texas Instruments PCA9548 1-to-8 channel I C switch (U52).

  • Page 48: Ac701 Board Leds

    IIC_SDA/SCL_DDR3 0b1010000, 0b0011000 SI5324_SDA/SCL 0b1101000 Information about the PCA9548 is available on the TI Semiconductor website [Ref AC701 Board LEDs Table 1-23 lists all LEDs on the AC701 board. Table 1-23: AC701 Board LEDs Reference Schematic Description Notes Designator Page...

  • Page 49: User I/O

    1. The Lumex SML-LX0603GW LED is Green User I/O [Figure 1-2, callout - 25] The AC701 board provides the following user and general purpose I/O capabilities: • Four user GPIO LEDs (callout 21) • GPIO_LED_[3-0]: DS5, DS4, DS3, DS2 •...
  • Page 50 Chapter 1: AC701 Evaluation Board Features User GPIO LEDs [Figure 1-2, callout 21] Figure 1-29 shows the user LED circuits. X-Ref Target - Figure 1-29 GPIO_LED_0 GPIO_LED_1 GPIO_LED_2 GPIO_LED_3 R150 R149 R148 R147 49.9Ω 49.9Ω 49.9Ω 49.9Ω UG952_c1_28_100312 Figure 1-29: User LEDs...
  • Page 51 X-Ref Target - Figure 1-33 SW10 VCC3V3 EVQ-WK4001 Edge-Drive Jog Encoder ROTARY INCB ROTARY PUSH SW1B SW1A ROTARY INCA 4.7kΩ 4.7kΩ 4.7kΩ 0.1 W 0.1 W 0.1 W UG952_c1_141_011813 Figure 1-33: User Rotary Switch Circuit AC701 Evaluation Board www.xilinx.com UG952 (v1.2) August 28, 2013...
  • Page 52 Chapter 1: AC701 Evaluation Board Features User SMA Connectors [Figure 1-2, callout 25] Figure 1-34 shows the user SMA connector circuit. X-Ref Target - Figure 1-34 USER_SMA_GPIO_P Connector USER_SMA_GPIO_N Connector UG952_c1_142_011813 Figure 1-34: User SMA Connector LCD Connector Figure 1-35 shows the LCD J23 2x7 male pin header circuit.
  • Page 53 4-Pole DIP Switch (Active High) GPIO_DIP_SW0 SW2.1 GPIO_DIP_SW1 SW2.2 GPIO_DIP_SW2 SW2.3 GPIO_DIP_SW3 SW2.4 Rotary Encoder Switch (Active High) ROTARY_INCB SW10.6 ROTARY_PUSH SW10.5 ROTARY_INCA SW10.1 User SMA Connectors USER_SMA_GPIO_P J33.1 USER_SMA_GPIO_N J34.1 AC701 Evaluation Board www.xilinx.com UG952 (v1.2) August 28, 2013...

  • Page 54: Switches

    [Figure 1-2, callout 26] The AC701 board power switch is SW15. Sliding the switch actuator from the Off to On position applies 12V power from J49, a 6-pin mini-fit connector. Green LED DS22 illuminates when the AC701 board power is on. See...
  • Page 55 The AC701 Evaluation Kit provides the adapter cable shown in Figure 1-38 for powering the AC701 board from the ATX power supply 4-pin peripheral connector. The Xilinx part number for this cable is 2600304, and is equivalent to Sourcegate Technologies part number AZCBL-WH-1109-RA4.

  • Page 56: Fpga Mezzanine Card Interface

    Chapter 1: AC701 Evaluation Board Features Configuration Mode Switch SW1 The AC701 board supports two of the five 7 series FPGA configuration modes: • Master SPI using the on-board Quad SPI flash memory • JTAG using a standard-A to micro-B USB cable for connecting the host PC to the...
  • Page 57 2 differential clocks • 159 ground and 15 power connections Note: The AC701 board VADJ voltage for HPC connector J30 is determined by the FMC VADJ power sequencing logic described in Power Management, page Table 1-26: HPC Connections, J30 to FPGA U1...
  • Page 58 Chapter 1: AC701 Evaluation Board Features Table 1-26: HPC Connections, J30 to FPGA U1 (Cont’d) J30 FMC U1 FPGA J30 FMC U1 FPGA Schematic Net Name Schematic Net Name HPC Pin HPC Pin FMC1_HPC_DP1_C2M_P FMC1_HPC_GBTCLK1_M2C_N U4.25 FMC1_HPC_DP1_C2M_N FMC1_HPC_DP0_C2M_P CTRL2_PWRGOOD FMC1_HPC_DP0_C2M_N FMC1_HPC_GBTCLK0_M2C_P U3.27...
  • Page 59 AF25 FMC1_HPC_HA09_N AF20 FMC1_HPC_HA08_P AD21 FMC1_HPC_HA13_P AC18 FMC1_HPC_HA08_N AE21 FMC1_HPC_HA13_N AD18 FMC1_HPC_HA12_P AC19 FMC1_HPC_HA16_P AE17 FMC1_HPC_HA12_N AD19 FMC1_HPC_HA16_N AF17 FMC1_HPC_HA15_P FMC1_HPC_HA20_P FMC1_HPC_HA15_N AA18 FMC1_HPC_HA20_N FMC1_HPC_HA19_P AC17 FMC1_HPC_HA19_N AD17 VCCO_VADJ VCCO_VADJ FMC1_HPC_CLK1_M2C_P AC701 Evaluation Board www.xilinx.com UG952 (v1.2) August 28, 2013...
  • Page 60 Chapter 1: AC701 Evaluation Board Features Table 1-26: HPC Connections, J30 to FPGA U1 (Cont’d) J30 FMC U1 FPGA J30 FMC U1 FPGA Schematic Net Name Schematic Net Name HPC Pin HPC Pin FMC1_HPC_CLK1_M2C_N FMC1_HPC_PRSNT_M2C FMC1_HPC_LA00_CC_P FMC1_HPC_CLK0_M2C_P FMC1_HPC_LA00_CC_N FMC1_HPC_CLK0_M2C_N FMC1_HPC_LA03_P...

  • Page 61: Ac701 Board Power System

    FMC1_HPC_HA23_N FMC1_VIO_B_M2C FMC1_VIO_B_M2C AC701 Board Power System The AC701 board hosts a power system based on the Texas Instruments (TI) UCD90120A power supply sequencer and monitor, and the TPS84K and LMZ22000 family voltage regulators. UCD90120A Description The UCD90120A is a 12-rail PMBus/I C addressable power-supply sequencer and monitor.
  • Page 62 The sync input allows synchronization over the 314 kHz to 600 kHz switching frequency range and up to 6 modules can be connected in parallel for higher load currents. Table 1-27 shows the AC701 board power system configuration for controller U8. Table 1-27: Controller U8 Power System Configuration Schematic Sequencer...
  • Page 63 CS = 0V-2.03V ADC (In) Notes: 1. Capacitors labled C f are bulk filter capacitors. 2. Voltage Sense is connected at point of load. UG952_c1_137_011513 Figure 1-41: U8 Controller #1 UCD90120A Power System AC701 Evaluation Board www.xilinx.com UG952 (v1.2) August 28, 2013...
  • Page 64 Chapter 1: AC701 Evaluation Board Features Table 1-28 shows the AC701 TI power system configuration for controller U9. Table 1-28: Controller U9 Power System Configuration Schematic Sequencer Regulator Type Voltage Current Page Page Contents Net Name UCD90120A #2 Addr 102, Rail 1...
  • Page 65 GPIO (Out) PWM Margin FPWM (Out) G = 268.4 Current Sense MGTAVTT ADC (In) 0A-1.5A Voltage Sense CS = 0V-2.02V ADC (In) UG952_c1_138_011513 Figure 1-42: U9 Controller #2 UCD90120A Power System AC701 Evaluation Board www.xilinx.com UG952 (v1.2) August 28, 2013...

  • Page 66: Xadc Power System Measurement

    The TPS84K and LMZ22000 family adjustable voltage regulators have their output voltage set by an external resistor. The regulator topology on the AC701 board permits the UCD90120A to monitor rail voltage and current. Voltage margining at +5% and -5% is also implemented.
  • Page 67 3.01 K Notes: FPGA_3V3_XADC_P 1.._XADC_P/N =Remote voltage sense. (3.3V Scaled to 0.825V) 2.._XADC_CS_P/N = Current Sense from op amp. 1.00 K FPGA_3V3_XADC_N UG952_c1_139_011813 Figure 1-43: XADC External Multiplexer Block Diagram AC701 Evaluation Board www.xilinx.com UG952 (v1.2) August 28, 2013...
  • Page 68 Chapter 1: AC701 Evaluation Board Features See Tables Table 1-29 Table 1-30 which list the AC701 board XADC power system voltage and current measurement details for the external muxes U14 and U13. Table 1-29: XADC Measurements through Mux U14 Op Amp...

  • Page 69: Power Management

    [Figure 1-2, callout 30] The AC701 board uses power regulators and PMBus compliant system controllers from Texas Instruments to supply core and auxiliary voltages. The Texas Instruments Fusion Digital Power graphical user interface is used to monitor the voltage and current levels of the board power modules.
  • Page 70 1.7V–2.0V at 300 mA 1.5V/2=0.75V REFIN VTTDDR Source/Sink Regulator 3.3V POWER 0.75V at 3A 1.5V/2=0.75V REFIN DDR3_VTERM Switching Regulator 3.3V POWER 0.75V at 3A UG952_c1_37_100512 Figure 1-44: AC701 Board Onboard Power Regulators www.xilinx.com AC701 Evaluation Board UG952 (v1.2) August 28, 2013...
  • Page 71 Feature Descriptions The AC701 board core and auxiliary voltages are listed in Table 1-25. Table 1-31: AC701 Board Onboard Power System Devices Reference Power Rail Net Power Rail Schematic Device Type Description Designator Name Voltage Page UCD90120A PMBus Controller - PMBus Addr = 101...
  • Page 72 A jumper installed at J8 is the default setting. If a jumper is not installed on J8 at power-on, the signal FMC_VADJ_ON_B is high and the AC701 board will not energize the VCCO_VADJ 2.5V power. Installing a jumper at J8 after the AC701 board powers up in this mode will turn on the VCCO_VADJ rail. www.xilinx.com AC701 Evaluation Board UG952 (v1.2) August 28, 2013...
  • Page 73 VCCO_VADJ rail to be set to 1.8V or 3.3V instead of the default setting of 2.5V. Refer to AC701 board schematic page 46 for a brief discussion concerning selectable VCCO_VADJ voltages. The important controller-to-regulator circuit signals are VCCO_VADJ_EN and FMC_ADJ_SEL[1:0].

  • Page 74: Xadc Header

    Chapter 1: AC701 Evaluation Board Features X-Ref Target - Figure 1-45 VCC12_P R245 R393 10.0K 1% 10.0K 1% 1/10W 1/10W SM_FAN_TACH FPGA Fan Tach U1 Pin J25 Cooling Fan +12V R390 2.7V 4.75K 1% Fan GND 500 mW 100V 1/10W...
  • Page 75 UG952_c1_39_101612 Figure 1-46: Header XADC_VREF Voltage Source Options The AC701 board supports both the internal FPGA sensor measurements and the external measurement capabilities of the XADC. Internal measurements of the die temperature, VCCINT, VCCAUX, and VCCBRAM are available. The AC701 board VCCINT and VCCBRAM are provided by a common 1.0 V supply.
  • Page 76 Chapter 1: AC701 Evaluation Board Features X-Ref Target - Figure 1-47 XADC_VP XADC_VN XADC_VAUX0P XADC_VAUX0N XADC_VCC5V0 XADC_VAUX8P XADC_VAUX8N XADC_DXP VCCO_VADJ XADC_VREF XADC_DXN XADC_VCC_HEADER XADC_GPIO_1 XADC_GPIO_0 XADC_GPIO_2 XADC_GPIO_3 XADC_AGND XADC_AGND UG952_c1_40_101612 Figure 1-47: XADC header (J19) Table 1-35 describes the XADC header J19 pin functions.

  • Page 77: Configuration Options

    Configuration Options Configuration Options The FPGA on the AC701 board can be configured using these methods: • Master SPI (uses the Quad-SPI Flash U7). • JTAG (uses the U26 Digilent USB-to-JTAG Bridge or J4 Download Cable connector). USB JTAG Module, page 19 for more information.
  • Page 78 4.7K VCC3V3 R396 CCLK 261Ω DONE DS10 D[3:0] GREEN Bank 14 FCS_B N25Q256A13ESF40G QUAD SPI DQ[1:0] DQ2_WP DQ3_HOLD_B Oscillator EMCCLK 90 MHz SIT8103 UG952_c1_42_072513 Figure 1-49: AC701 Board QSPI Configuration Circuit www.xilinx.com AC701 Evaluation Board UG952 (v1.2) August 28, 2013...

  • Page 79: Appendix A: Default Switch And Jumper Settings

    X-Ref Target - Figure A-1 ON Position = 1 2 3 4 OFF Position = 0 UG952_aA_01_100712 Figure A-1: SW2 Default Settings Table A-1: SW2 Default Switch Settings Position Function Default GPIO_DIP_SW0 GPIO_DIP_SW1 GPIO_DIP_SW2 GPIO_DIP_SW3 AC701 Evaluation Board www.xilinx.com UG952 (v1.2) August 28, 2013...

  • Page 80: Configuration Dip Switch Sw1

    Figure A-2: SW1 Default Settings The default mode setting M[2:0] = 001 selects Master SPI configuration at board power-on. Table A-2: SW1 Default Switch Settings Position Function Default FPGA_M2 FPGA_M1 FPGA_M0 www.xilinx.com AC701 Evaluation Board UG952 (v1.2) August 28, 2013...

  • Page 81: Default Jumper Settings

    Default Jumper Settings Default Jumper Settings The AC701 board default jumper configurations are listed in Table A-3. Table A-3: AC701 Default Jumper Settings Schematic Header Jumper Description Page 2-pin XADC VCCINT 4A range XADC_VCC5V0 = 5V REF3012 XADC_AGND L3 bypassed...
  • Page 82 Appendix A: Default Switch and Jumper Settings www.xilinx.com AC701 Evaluation Board UG952 (v1.2) August 28, 2013...

  • Page 83: Appendix B: Vita 57.1 Fmc Connector Pinouts

    Figure B-1 shows the pinout of the FPGA mezzanine card (FMC) high pin count (HPC) connector defined by the VITA 57.1 FMC specification. For a description of how the AC701 board implements the FMC specification, see FPGA Mezzanine Card Interface, page 56...
  • Page 84 Appendix B: VITA 57.1 FMC Connector Pinouts www.xilinx.com AC701 Evaluation Board UG952 (v1.2) August 28, 2013...

  • Page 85: Appendix C: Master Constraints File Listing

    Appendix C Master Constraints File Listing TheAC701 board master Xilinx® design constraints (XDC) file template provides for designs targeting the AC701 board. Net names in the constraints listed in the AC701 Board XDC File Listing correlate with net names on the AC701 board schematic. Users must identify the appropriate pins and replace the net names in this list with net names in the user RTL.
  • Page 86 #MGTs set_property PACKAGE_PIN AB13 [get_ports SFP_MGT_CLK0_N] set_property IOSTANDARD LVDS_25 [get_ports SFP_MGT_CLK0_N] set_property PACKAGE_PIN AA13 [get_ports SFP_MGT_CLK0_P] set_property IOSTANDARD LVDS_25 [get_ports SFP_MGT_CLK0_P] set_property PACKAGE_PIN AA11 [get_ports SFP_MGT_CLK1_P] set_property IOSTANDARD LVDS_25 [get_ports SFP_MGT_CLK1_P] www.xilinx.com AC701 Evaluation Board UG952 (v1.2) August 28, 2013...
  • Page 87 AC701 Board XDC File Listing set_property PACKAGE_PIN AB11 [get_ports SFP_MGT_CLK1_N] set_property IOSTANDARD LVDS_25 [get_ports SFP_MGT_CLK1_N] set_property PACKAGE_PIN E11 [get_ports PCIE_CLK_QO_N] set_property IOSTANDARD LVDS_25 [get_ports PCIE_CLK_QO_N] set_property PACKAGE_PIN F11 [get_ports PCIE_CLK_QO_P] set_property IOSTANDARD LVDS_25 [get_ports PCIE_CLK_QO_P] #FMC1 set_property PACKAGE_PIN N16 [get_ports FMC1_HPC_PRSNT_M2C_B]...
  • Page 88 IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA24_N] set_property PACKAGE_PIN G22 [get_ports FMC1_HPC_LA25_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA25_P] set_property PACKAGE_PIN F22 [get_ports FMC1_HPC_LA25_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA25_N] set_property PACKAGE_PIN J24 [get_ports FMC1_HPC_LA26_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA26_P] www.xilinx.com AC701 Evaluation Board UG952 (v1.2) August 28, 2013...
  • Page 89 AC701 Board XDC File Listing set_property PACKAGE_PIN H24 [get_ports FMC1_HPC_LA26_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA26_N] set_property PACKAGE_PIN F23 [get_ports FMC1_HPC_LA27_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA27_P] set_property PACKAGE_PIN E23 [get_ports FMC1_HPC_LA27_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA27_N] set_property PACKAGE_PIN K22 [get_ports FMC1_HPC_LA28_P]...
  • Page 90 IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA22_P] set_property PACKAGE_PIN AA15 [get_ports FMC1_HPC_HA22_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA22_N] set_property PACKAGE_PIN W14 [get_ports FMC1_HPC_HA23_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA23_P] set_property PACKAGE_PIN W15 [get_ports FMC1_HPC_HA23_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA23_N] www.xilinx.com AC701 Evaluation Board UG952 (v1.2) August 28, 2013...
  • Page 91 AC701 Board XDC File Listing #HDMI set_property PACKAGE_PIN AA24 [get_ports HDMI_R_D4] set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D4] set_property PACKAGE_PIN Y25 [get_ports HDMI_R_D5] set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D5] set_property PACKAGE_PIN Y26 [get_ports HDMI_R_D6] set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D6] set_property PACKAGE_PIN V26 [get_ports HDMI_R_D7]...
  • Page 92 IOSTANDARD LVCMOS33 [get_ports LCD_DB4_LS] set_property PACKAGE_PIN M24 [get_ports LCD_DB5_LS] set_property IOSTANDARD LVCMOS33 [get_ports LCD_DB5_LS] set_property PACKAGE_PIN M25 [get_ports LCD_DB6_LS] set_property IOSTANDARD LVCMOS33 [get_ports LCD_DB6_LS] set_property PACKAGE_PIN L22 [get_ports LCD_DB7_LS] set_property IOSTANDARD LVCMOS33 [get_ports LCD_DB7_LS] www.xilinx.com AC701 Evaluation Board UG952 (v1.2) August 28, 2013...
  • Page 93 AC701 Board XDC File Listing #ROTARY set_property PACKAGE_PIN N21 [get_ports ROTARY_PUSH] set_property IOSTANDARD LVCMOS33 [get_ports ROTARY_PUSH] set_property PACKAGE_PIN N22 [get_ports ROTARY_INCA] set_property IOSTANDARD LVCMOS33 [get_ports ROTARY_INCA] set_property PACKAGE_PIN P20 [get_ports ROTARY_INCB] set_property IOSTANDARD LVCMOS33 [get_ports ROTARY_INCB] #LEDs set_property PACKAGE_PIN M26 [get_ports GPIO_LED_0]...
  • Page 94 PACKAGE_PIN P1 [get_ports DDR3_RAS_B] set_property IOSTANDARD SSTL15 [get_ports DDR3_RAS_B] set_property PACKAGE_PIN T4 [get_ports DDR3_CAS_B] set_property IOSTANDARD SSTL15 [get_ports DDR3_CAS_B] set_property PACKAGE_PIN T3 [get_ports DDR3_S0_B] set_property IOSTANDARD SSTL15 [get_ports DDR3_S0_B] set_property PACKAGE_PIN T2 [get_ports DDR3_S1_B] www.xilinx.com AC701 Evaluation Board UG952 (v1.2) August 28, 2013...
  • Page 95 AC701 Board XDC File Listing set_property IOSTANDARD SSTL15 [get_ports DDR3_S1_B] set_property PACKAGE_PIN R2 [get_ports DDR3_ODT0] set_property IOSTANDARD SSTL15 [get_ports DDR3_ODT0] set_property PACKAGE_PIN U2 [get_ports DDR3_ODT1] set_property IOSTANDARD SSTL15 [get_ports DDR3_ODT1] set_property PACKAGE_PIN U1 [get_ports DDR3_TEMP_EVENT] set_property IOSTANDARD LVCMOS15 [get_ports DDR3_TEMP_EVENT]...
  • Page 96 PACKAGE_PIN E1 [get_ports DDR3_D34] set_property IOSTANDARD SSTL15 [get_ports DDR3_D34] set_property PACKAGE_PIN E2 [get_ports DDR3_D35] set_property IOSTANDARD SSTL15 [get_ports DDR3_D35] set_property PACKAGE_PIN F2 [get_ports DDR3_D36] set_property IOSTANDARD SSTL15 [get_ports DDR3_D36] set_property PACKAGE_PIN A2 [get_ports DDR3_D37] www.xilinx.com AC701 Evaluation Board UG952 (v1.2) August 28, 2013...
  • Page 97 AC701 Board XDC File Listing set_property IOSTANDARD SSTL15 [get_ports DDR3_D37] set_property PACKAGE_PIN A3 [get_ports DDR3_D38] set_property IOSTANDARD SSTL15 [get_ports DDR3_D38] set_property PACKAGE_PIN C2 [get_ports DDR3_D39] set_property IOSTANDARD SSTL15 [get_ports DDR3_D39] set_property PACKAGE_PIN C3 [get_ports DDR3_D40] set_property IOSTANDARD SSTL15 [get_ports DDR3_D40]...
  • Page 98 IOSTANDARD SSTL15 [get_ports DDR3_A15] set_property PACKAGE_PIN N1 [get_ports DDR3_BA0] set_property IOSTANDARD SSTL15 [get_ports DDR3_BA0] set_property PACKAGE_PIN M1 [get_ports DDR3_BA1] set_property IOSTANDARD SSTL15 [get_ports DDR3_BA1] set_property PACKAGE_PIN H2 [get_ports DDR3_BA2] set_property IOSTANDARD SSTL15 [get_ports DDR3_BA2] www.xilinx.com AC701 Evaluation Board UG952 (v1.2) August 28, 2013...

  • Page 99: Appendix D: Board Setup

    Figure D-1: Plug the 6-pin 2 x 3 Molex connector on the adapter cable into J49 on the AC701 board. b. Plug the 4-pin 1 x 4 peripheral power connector from the ATX power supply into the 4-pin adapter cable connector.
  • Page 100 Appendix D: Board Setup Slide the AC701 board power switch SW15 to the ON position. The PC can now be powered on. www.xilinx.com AC701 Evaluation Board UG952 (v1.2) August 28, 2013...

  • Page 101: Appendix E: Board Specifications

    Board Specifications Dimensions Height 5.5 in (14.0 cm) Length 10.5 in (26.7 cm) Note: The AC701 board height exceeds the standard 4.376 in (11.15 cm) height of a PCI Express card. Environmental Temperature Operating: 0°C to +45°C Storage: –25°C to +60°C...
  • Page 102 Appendix E: Board Specifications www.xilinx.com AC701 Evaluation Board UG952 (v1.2) August 28, 2013...

  • Page 103: Appendix F: Additional Resources

    Topics include design assistance, advisories, and troubleshooting tips. Further Resources The most up to date information related to the AC701 board and its documentation is available on the following websites. Artix-7 FPGA AC701 Evaluation Kit website...

  • Page 104: References

    Appendix F: Additional Resources AC701 Si570 Fixed Frequencies (XTP229) References Documents associated with other devices used by the AC701 board are available at these vendor websites: Analog Devices: www.analog.com/en/index (ADV7511KSTZ-P) Integrated Device Technology: www.idt.com (ICS844021I) Marvell Semiconductor: www.marvell.com (88E1116R) Micron Semiconductor: www.micron.com...

  • Page 105: Appendix G: Regulatory And Compliance Information

    This product is designed and tested to conform to the European Union directives and standards described in this section. Refer to the Artix-7 FPGA AC701 Evaluation Kit Master Answer Record (AR 51900) concerning the CE requirements for the PC Test Environment. Declaration of Conformity To view the declaration of conformity online, visit: www.xilinx.com/support/documentation/boards_and_kits/ce-declarations-...

  • Page 106: Markings

    This product complies with Directive 2002/95/EC on the restriction of hazardous substances (RoHS) in electrical and electronic equipment. This product complies with CE Directives 2006/95/EC, Low Voltage Directive (LVD) and 2004/108/EC, Electromagnetic Compatibility (EMC) Directive. www.xilinx.com AC701 Evaluation Board UG952 (v1.2) August 28, 2013...

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