Xilinx AC701 User Manual page 15

Table 1-4: DDR3 Memory Connections to the FPGA (Cont'd)
AC701 Evaluation Board
UG952 (v1.2) August 28, 2013
U1 FPGA Pin Net Name
AC4 DDR3_DM1
AA3 DDR3_DM2
U7 DDR3_DM3
G1 DDR3_DM4
F3 DDR3_DM5
G5 DDR3_DM6
H9 DDR3_DM7
W8 DDR3_DQS0_N
V8 DDR3_DQS0_P
AE5 DDR3_DQS1_N
AD5 DDR3_DQS1_P
AE1 DDR3_DQS2_N
AD1 DDR3_DQS2_P
V2 DDR3_DQS3_N
V3 DDR3_DQS3_P
B1 DDR3_DQS4_N
C1 DDR3_DQS4_P
A5 DDR3_DQS5_N
B5 DDR3_DQS5_P
H4 DDR3_DQS6_N
J4 DDR3_DQS6_P
G7 DDR3_DQS7_N
H7 DDR3_DQS7_P
R2 DDR3_ODT0
U2 DDR3_ODT1
N8 DDR3_RESET_B
T3 DDR3_S0_B
T2 DDR3_S1_B
DDR3_TEMP_
U1
EVENT
R1 DDR3_WE_B
T4 DDR3_CAS_B
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J1 DDR3 Memory
Pin Number Pin Name
28 DM1
46 DM2
63 DM3
136 DM4
153 DM5
170 DM6
187 DM7
10 DQS0_N
12 DQS0_P
27 DQS1_N
29 DQS1_P
45 DQS2_N
47 DQS2_P
62 DQS3_N
64 DQS3_P
135 DQS4_N
137 DQS4_P
152 DQS5_N
154 DQS5_P
169 DQS6_N
171 DQS6_P
186 DQS7_N
188 DQS7_P
116 ODT0
120 ODT1
30 RESET_B
114 S0_B
121 S1_B
198 EVENT_B
113 WE_B
115 CAS_B
Feature Descriptions
15