Xilinx AC701 User Manual page 92

Appendix C: Master Constraints File Listing
92
#ETHERNET
set_property PACKAGE_PIN V18 [get_ports PHY_RESET_B]
set_property IOSTANDARD LVCMOS18 [get_ports PHY_RESET_B]
set_property PACKAGE_PIN W18 [get_ports PHY_MDC]
set_property IOSTANDARD LVCMOS18 [get_ports PHY_MDC]
set_property PACKAGE_PIN T14 [get_ports PHY_MDIO]
set_property IOSTANDARD LVCMOS18 [get_ports PHY_MDIO]
set_property PACKAGE_PIN U22 [get_ports PHY_TX_CLK]
set_property IOSTANDARD LVCMOS18 [get_ports PHY_TX_CLK]
set_property PACKAGE_PIN U21 [get_ports PHY_RX_CLK]
set_property IOSTANDARD LVCMOS18 [get_ports PHY_RX_CLK]
set_property PACKAGE_PIN T15 [get_ports PHY_TX_CTRL]
set_property IOSTANDARD LVCMOS18 [get_ports PHY_TX_CTRL]
set_property PACKAGE_PIN U14 [get_ports PHY_RX_CTRL]
set_property IOSTANDARD LVCMOS18 [get_ports PHY_RX_CTRL]
set_property PACKAGE_PIN U16 [get_ports PHY_TXD0]
set_property IOSTANDARD LVCMOS18 [get_ports PHY_TXD0]
set_property PACKAGE_PIN U17 [get_ports PHY_RXD0]
set_property IOSTANDARD LVCMOS18 [get_ports PHY_RXD0]
set_property PACKAGE_PIN U15 [get_ports PHY_TXD1]
set_property IOSTANDARD LVCMOS18 [get_ports PHY_TXD1]
set_property PACKAGE_PIN V17 [get_ports PHY_RXD1]
set_property IOSTANDARD LVCMOS18 [get_ports PHY_RXD1]
set_property PACKAGE_PIN T18 [get_ports PHY_TXD2]
set_property IOSTANDARD LVCMOS18 [get_ports PHY_TXD2]
set_property PACKAGE_PIN V16 [get_ports PHY_RXD2]
set_property IOSTANDARD LVCMOS18 [get_ports PHY_RXD2]
set_property PACKAGE_PIN T17 [get_ports PHY_TXD3]
set_property IOSTANDARD LVCMOS18 [get_ports PHY_TXD3]
set_property PACKAGE_PIN V14 [get_ports PHY_RXD3]
set_property IOSTANDARD LVCMOS18 [get_ports PHY_RXD3]
#UART
set_property PACKAGE_PIN T19 [get_ports USB_UART_TX]
set_property IOSTANDARD LVCMOS18 [get_ports USB_UART_TX]
set_property PACKAGE_PIN U19 [get_ports USB_UART_RX]
set_property IOSTANDARD LVCMOS18 [get_ports USB_UART_RX]
set_property PACKAGE_PIN V19 [get_ports USB_UART_RTS]
set_property IOSTANDARD LVCMOS18 [get_ports USB_UART_RTS]
set_property PACKAGE_PIN W19 [get_ports USB_UART_CTS]
set_property IOSTANDARD LVCMOS18 [get_ports USB_UART_CTS]
#GPIO
#LCD
set_property PACKAGE_PIN L20 [get_ports LCD_E_LS]
set_property IOSTANDARD LVCMOS33 [get_ports LCD_E_LS]
set_property PACKAGE_PIN L24 [get_ports LCD_RW_LS]
set_property IOSTANDARD LVCMOS33 [get_ports LCD_RW_LS]
set_property PACKAGE_PIN L23 [get_ports LCD_RS_LS]
set_property IOSTANDARD LVCMOS33 [get_ports LCD_RS_LS]
set_property PACKAGE_PIN L25 [get_ports LCD_DB4_LS]
set_property IOSTANDARD LVCMOS33 [get_ports LCD_DB4_LS]
set_property PACKAGE_PIN M24 [get_ports LCD_DB5_LS]
set_property IOSTANDARD LVCMOS33 [get_ports LCD_DB5_LS]
set_property PACKAGE_PIN M25 [get_ports LCD_DB6_LS]
set_property IOSTANDARD LVCMOS33 [get_ports LCD_DB6_LS]
set_property PACKAGE_PIN L22 [get_ports LCD_DB7_LS]
set_property IOSTANDARD LVCMOS33 [get_ports LCD_DB7_LS]
www.xilinx.com AC701 Evaluation Board
UG952 (v1.2) August 28, 2013