Xilinx AC701 User Manual page 98

Appendix C: Master Constraints File Listing
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set_property PACKAGE_PIN K1 [get_ports DDR3_A6]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A6]
set_property PACKAGE_PIN M6 [get_ports DDR3_A7]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A7]
set_property PACKAGE_PIN H1 [get_ports DDR3_A8]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A8]
set_property PACKAGE_PIN K3 [get_ports DDR3_A9]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A9]
set_property PACKAGE_PIN N7 [get_ports DDR3_A10]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A10]
set_property PACKAGE_PIN L5 [get_ports DDR3_A11]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A11]
set_property PACKAGE_PIN L7 [get_ports DDR3_A12]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A12]
set_property PACKAGE_PIN N6 [get_ports DDR3_A13]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A13]
set_property PACKAGE_PIN L3 [get_ports DDR3_A14]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A14]
set_property PACKAGE_PIN K2 [get_ports DDR3_A15]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A15]
set_property PACKAGE_PIN N1 [get_ports DDR3_BA0]
set_property IOSTANDARD SSTL15 [get_ports DDR3_BA0]
set_property PACKAGE_PIN M1 [get_ports DDR3_BA1]
set_property IOSTANDARD SSTL15 [get_ports DDR3_BA1]
set_property PACKAGE_PIN H2 [get_ports DDR3_BA2]
set_property IOSTANDARD SSTL15 [get_ports DDR3_BA2]
www.xilinx.com AC701 Evaluation Board
UG952 (v1.2) August 28, 2013