ST STM32G4 Series Reference Manual page 1000

High-resolution timer (HRTIM)
Bit 5 Reserved, must be kept at reset value.
Bits 4:1 EE1FLTR[3:0]: External event 1 filter
0000: No filtering
0001: Blanking from counter reset/roll-over to compare 1
0010: Blanking from counter reset/roll-over to compare 2 in up-counting mode (UDM bit reset)
In up-down counting mode (UDM bit set): blanking from compare 1 to compare 2, only during
the up-counting phase.
0011: Blanking from counter reset/roll-over to compare 3
0100: Blanking from counter reset/roll-over to compare 4
0100: Blanking from counter reset/roll-over to compare 4 in up-counting mode (UDM bit reset)
In up-down counting mode (UDM bit set): blanking from compare 3 to compare 4, only during
the up-counting phase.
0101: Blanking from another timing unit: TIMFLTR1 source (see
0110: Blanking from another timing unit: TIMFLTR2 source (see
0111: Blanking from another timing unit: TIMFLTR3 source (see
1000: Blanking from another timing unit: TIMFLTR4 source (see
1001: Blanking from another timing unit: TIMFLTR5 source (see
1010: Blanking from another timing unit: TIMFLTR6 source (see
1011: Blanking from another timing unit: TIMFLTR7 source (see
1100: Blanking from another timing unit: TIMFLTR8 source (see
1101: Windowing from counter reset/roll-over to compare 2 in up-counting mode (UDM bit reset)
In up-down counting mode (UDM bit set): windowing from compare 2 to compare 3, only
during the up-counting phase.
1110: Windowing from counter reset/roll-over to compare 3 in up-counting mode (UDM bit reset)
In up-down counting mode (UDM bit set): windowing from compare 2 to compare 3, only
during the down-counting phase.
1111: Windowing from another timing unit: TIMWIN source (see
counting mode (UDM bit reset)
In up-down counting mode (UDM bit set): windowing from compare 2 during the up-counting
phase to compare 3 during the down-counting phase.
Note: Whenever a compare register is used for filtering, the value must be strictly above 0.
This bitfield must not be modified once the counter is enabled (TxCEN bit set)
Bit 0 EE1LTCH: External event 1 latch
0: Event 1 is ignored if it happens during a blank, or passed through during a window.
1: Event 1 is latched and delayed till the end of the blanking or windowing period.
Note: A timeout event is generated in window mode (EE1FLTR[3:0]=1101, 1110, 1111) if
EE1LTCH = 0, except if the external event is programmed in fast mode (EExFAST = 1).
This bitfield must not be modified once the counter is enabled (TxCEN bit set).
1000/2126 RM0440 Rev 4
Table 224 for details)
Table 224 for details)
Table 224 for details)
Table 224 for details)
Table 224 for details)
Table 224 for details)
Table 224 for details)
Table 224 for details)
Table 225 for details) in up-
RM0440