ST STM32G4 Series Reference Manual page 710

Analog-to-digital converters (ADC)
Bits 8:7 JEXTEN[1:0]: External Trigger Enable and Polarity Selection for injected channels
Note: The software is allowed to write these bits only when JADSTART=0 (which ensures that
Bits 6:2 JEXTSEL[4:0]: External Trigger Selection for injected group
Note: The software is allowed to write these bits only when JADSTART=0 (which ensures that
Bits 1:0 JL[1:0]: Injected channel sequence length
Note: The software is allowed to write these bits only when JADSTART=0 (which ensures that
Note: Some channels are not connected physically and must not be selected for conversion.
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These bits are set and cleared by software to select the external trigger polarity and enable
the trigger of an injected group.
00: If JQDIS=0 (queue enabled), Hardware and software trigger detection disabled
00: If JQDIS=1 (queue disabled), Hardware trigger detection disabled (conversions can be
launched by software)
01: Hardware trigger detection on the rising edge
10: Hardware trigger detection on the falling edge
11: Hardware trigger detection on both the rising and falling edges
no injected conversion is ongoing).
If JQM=1 and if the Queue of Context becomes empty, the software and hardware
triggers of the injected sequence are both internally disabled (refer to
Queue of context for injected
These bits select the external event used to trigger the start of conversion of an injected
group:
00000: Event 0
00001: Event 1
00010: Event 2
00011: Event 3
00100: Event 4
00101: Event 5
00110: Event 6
00111: Event 7
...
11111: Event 31
no injected conversion is ongoing).
These bits are written by software to define the total number of conversions in the injected
channel conversion sequence.
00: 1 conversion
01: 2 conversions
10: 3 conversions
11: 4 conversions
no injected conversion is ongoing).
conversions)
RM0440 Rev 4
RM0440
Section 21.4.21: