ST STM32G4 Series Reference Manual page 963

Advanced arm-based 32-bit mcus
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RM0440
27.5.3
HRTIM master timer interrupt clear register (HRTIM_MICR)
Address offset: 0x008
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:7 Reserved, must be kept at reset value.
Bit 6 MUPDC: Master update interrupt flag clear
Writing 1 to this bit clears the MUPDC flag in HRTIM_MISR register.
Bit 5 SYNCC: Sync input interrupt flag clear
Writing 1 to this bit clears the SYNC flag in HRTIM_MISR register.
Bit 4 MREPC: Repetition interrupt flag clear
Writing 1 to this bit clears the MREP flag in HRTIM_MISR register.
Bit 3 MCMP4C: Master compare 4 interrupt flag clear
Writing 1 to this bit clears the MCMP4 flag in HRTIM_MISR register.
Bit 2 MCMP3C: Master compare 3 interrupt flag clear
Writing 1 to this bit clears the MCMP3 flag in HRTIM_MISR register.
Bit 1 MCMP2C: Master compare 2 interrupt flag clear
Writing 1 to this bit clears the MCMP2 flag in HRTIM_MISR register.
Bit 0 MCMP1C: Master compare 1 interrupt flag clear
Writing 1 to this bit clears the MCMP1 flag in HRTIM_MISR register.
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
24
23
22
Res.
Res.
Res.
8
7
6
MUPD
Res.
Res.
SYNCC
C
w
RM0440 Rev 4
High-resolution timer (HRTIM)
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
MREP
MCMP
MCMP
C
4C
3C
w
w
w
w
17
16
Res.
Res.
1
0
MCMP
MCMP
2C
1C
w
w
963/2126
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