ST STM32G4 Series Reference Manual page 963

Advanced arm-based 32-bit mcus

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HRTIM master timer interrupt clear register (HRTIM_MICR)

Address offset: 0x008

Reset value: 0x0000 0000

Bits 31:7 Reserved, must be kept at reset value.

Bit 6 MUPDC: Master update interrupt flag clear

Writing 1 to this bit clears the MUPDC flag in HRTIM_MISR register.

Bit 5 SYNCC: Sync input interrupt flag clear

Writing 1 to this bit clears the SYNC flag in HRTIM_MISR register.

Bit 4 MREPC: Repetition interrupt flag clear

Writing 1 to this bit clears the MREP flag in HRTIM_MISR register.

Bit 3 MCMP4C: Master compare 4 interrupt flag clear

Writing 1 to this bit clears the MCMP4 flag in HRTIM_MISR register.

Bit 2 MCMP3C: Master compare 3 interrupt flag clear

Writing 1 to this bit clears the MCMP3 flag in HRTIM_MISR register.

Bit 1 MCMP2C: Master compare 2 interrupt flag clear

Writing 1 to this bit clears the MCMP2 flag in HRTIM_MISR register.

Bit 0 MCMP1C: Master compare 1 interrupt flag clear

Writing 1 to this bit clears the MCMP1 flag in HRTIM_MISR register.

RM0440 Rev 4

High-resolution timer (HRTIM)

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