ST STM32G4 Series Reference Manual page 1044

High-resolution timer (HRTIM)
Bit 17 TCCMP1: Timer C compare 1 event
Refer to TACMP1 description.
Bit 16 TCREP: Timer C repetition
Refer to TAREP description.
Bit 15 TCRST: Timer C reset or roll-over
Refer to TARST description.
Bit 14 TBCMP2: Timer B compare 2 event
Refer to TACMP1 description.
Bit 13 TBCMP1: Timer B compare 1 event
Refer to TACMP1 description.
Bit 12 TBREP: Timer B repetition
Refer to TAREP description.
Bit 11 TBRST: Timer B reset or roll-over
Refer to TARST description.
Bit 10 TACMP2: Timer A compare 2 event
Refer to TACMP1 description.
Bit 9 TACMP1: Timer A compare 1 event
The timer A compare 1 event is starting the burst mode operation.
Bit 8 TAREP: Timer A repetition
The Timer A repetition event is starting the burst mode operation.
Bit 7 TARST: Timer A reset or roll-over
The Timer A reset or roll-over event is starting the burst mode operation.
Bit 6 MSTCMP4: Master compare 4
Refer to MSTCMP1 description.
Bit 5 MSTCMP3: Master compare 3
Refer to MSTCMP1 description.
Bit 4 MSTCMP2: Master compare 2
Refer to MSTCMP1 description.
Bit 3 MSTCMP1: Master compare 1
The master timer compare 1 event is starting the burst mode operation.
Bit 2 MSTREP: Master repetition
The master timer repetition event is starting the burst mode operation.
Bit 1 MSTRST: Master reset or roll-over
The master timer reset and roll-over event is starting the burst mode operation.
Bit 0 SW: Software start
This bit is set by software and automatically reset by hardware.
When set, It starts the burst mode operation immediately.
This bit is not active if the burst mode is not enabled (BME bit is reset).
1044/2126 RM0440 Rev 4
RM0440