Table 318. Aes Internal Input/Output Signals; Figure 501. Aes Block Diagram - ST STM32G4 Series Reference Manual

AES hardware accelerator (AES)
34.3 AES implementation
The devices have one AES peripheral.
34.4 AES functional description
34.4.1 AES block diagram
Figure 501
32-bit
AHB bus
aes_hclk
aes_in_dma
aes_out_dma
34.4.2 AES internal signals
Table 318
Signal name
aes_hclk
aes_it
aes_in_dma
aes_out_dma
1490/2126
shows the block diagram of AES.

Figure 501. AES block diagram

AES
AHB
interface
DMA
interface
IRQ
aes_it
interface
describes the user relevant internal signals interfacing the AES peripheral.

Table 318. AES internal input/output signals

Signal type
Input
Output
Input/Output
Input/Output
32-bit
Banked registers
access
AES_KEYRx
key
AES_IVRx
IV, counter
status AES_SR
AES_CR
control
AES_DINR
data in
AES_DOUTR
data out
AES_SUSPRx
Control Logic
AHB bus clock
AES interrupt request
Input DMA single request/acknowledge
Output DMA single request/acknowledge
RM0440 Rev 4
KEY
IVI
swap
AES
DIN Core
(AEA)
DOUT
Save / Restore
Description
RM0440
MSv42154V1