Figure 418. Counter Reset Narrow Index Pulse (Closer View, Arr = 0X07) - ST STM32G4 Series Reference Manual
Advanced arm-based 32-bit mcus
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- Reference manual (2083 pages) ,
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RM0440
Figure 418. Counter reset Narrow index pulse (closer view, ARR = 0x07)
Channel A
Channel B
DIR bit
Counter
Channel A
Channel B
DIR bit
Counter
The
Figure 419
Index
5
6
Index
4
5
below shows how the index is managed in x1 and x2 modes.
General-purpose timers (TIM2/TIM3/TIM4/TIM5)
7
0
6
0
7
RM0440 Rev 4
1
2
3
1
2
3
1285/2126
MSv45772V1
1343
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