Figure 483. Counter Timing Diagram, Internal Clock Divided By 1; Figure 484. Counter Timing Diagram, Internal Clock Divided By 2 - ST STM32G4 Series Reference Manual

RM0440
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag

Figure 483. Counter timing diagram, internal clock divided by 1

tim_psc_ck
CEN
tim_cnt_ck
31
(UIF)

Figure 484. Counter timing diagram, internal clock divided by 2

tim_psc_ck
CEN
tim_cnt_ck
0034
(UIF)
32 34 35 36 00
33
0035 0036
RM0440 Rev 4
Basic timers (TIM6/TIM7)
01 02
03 04 05
0002
0000 0001
06 07
MSv50997V1
0003
MSv62300V1
1451/2126
1463