ST STM32G4 Series Reference Manual page 1194

Advanced-control timers (TIM1/TIM8/TIM20)
Bit 3 OC1PE: Output compare 1 preload enable
Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed
Bit 2 OC1FE: Output compare 1 fast enable
Bits 1:0 CC1S[1:0]: Capture/compare 1 selection
Note: CC1S bits are writable only when the channel is OFF (CC1E = '0' in TIMx_CCER).
28.6.9 TIMx capture/compare mode register 2 [alternate]
(TIMx_CCMR2)(x = 1, 8, 20)
Address offset: 0x01C
Reset value: 0x0000 0000
The same register can be used for input capture mode (this section) or for output compare
mode (next section). The direction of a channel is defined by configuring the corresponding
CCxS bits. All the other bits of this register have a different function for input capture and for
output compare modes. It is possible to combine both modes independently (e.g. channel 3
in input capture mode and channel 4 in output compare mode).
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
IC4F[3:0]
rw rw rw rw
Input capture mode
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0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new
value is taken in account immediately.
1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload
register. TIMx_CCR1 preload value is loaded in the active register at each update event.
(LOCK bits in TIMx_BDTR register) and CC1S='00' (the channel is configured in
output).
2: The PWM mode can be used without validating the preload register only in one
pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed.
This bit decreases the latency between a trigger event and a transition on the timer output.
It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output
pulse starting as soon as possible after the starting trigger.
0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is
ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input
is 5 clock cycles.
1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is
set to the compare level independently from the result of the comparison. Delay to sample
the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only
if the channel is configured in PWM1 or PWM2 mode.
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC1 channel is configured as output
01: CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1
10: CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2
11: CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. This mode is working
only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
27 26 25
Res. Res. Res.
11 10 9
IC4PSC[1:0] CC4S[1:0]
rw rw rw
24 23 22
Res. Res. Res. Res.
8 7 6
IC3F[3:0]
rw rw rw
RM0440 Rev 4
21 20 19 18
Res. Res. Res.
5 4 3 2
IC3PSC[1:0]
rw rw rw rw
RM0440
17 16
Res. Res.
1 0
CC3S[1:0]
rw rw