ST STM32G4 Series Reference Manual page 1314

General-purpose timers (TIM2/TIM3/TIM4/TIM5)
Bit 7 Reserved, must be kept at reset value.
Bit 6 TIE: Trigger interrupt enable
Bit 5 Reserved, must be kept at reset value.
Bit 4 CC4IE: Capture/Compare 4 interrupt enable
Bit 3 CC3IE: Capture/Compare 3 interrupt enable
Bit 2 CC2IE: Capture/Compare 2 interrupt enable
Bit 1 CC1IE: Capture/Compare 1 interrupt enable
Bit 0 UIE: Update interrupt enable
29.5.5 TIMx status register (TIMx_SR)(x = 2 to 5)
Address offset: 0x010
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. CC4OF CC3OF CC2OF CC1OF
rc_w0
Bits 31:24 Reserved, must be kept at reset value.
Bit 23 TERRF: Transition error interrupt flag
This flag is set by hardware when a transition error is detected in encoder mode. It is cleared
by software by writing it to '0'.
0: No encoder transition error has been detected.
1: An encoder transition error has been detected
Bit 22 IERRF: Index error interrupt flag
This flag is set by hardware when an index error is detected. It is cleared by software by
writing it to '0'.
0: No index error has been detected.
1: An index error has been detected
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0: Trigger interrupt disabled.
1: Trigger interrupt enabled.
0: CC4 interrupt disabled.
1: CC4 interrupt enabled.
0: CC3 interrupt disabled.
1: CC3 interrupt enabled.
0: CC2 interrupt disabled.
1: CC2 interrupt enabled.
0: CC1 interrupt disabled.
1: CC1 interrupt enabled.
0: Update interrupt disabled.
1: Update interrupt enabled.
28 27 26 25
Res. Res. Res.
12 11 10 9
rc_w0 rc_w0 rc_w0
24 23 22
Res. TERRF IERRF DIRF
rc_w0 rc_w0 rc_w0
8 7 6
Res. Res. TIF
rc_w0
RM0440 Rev 4
21 20 19 18
IDXF Res. Res.
rc_w0
5 4 3 2
Res. CC4IF CC3IF CC2IF
rc_w0 rc_w0 rc_w0
RM0440
17 16
Res. Res.
1 0
CC1IF UIF
rc_w0 rc_w0