ST STM32G4 Series Reference Manual page 1215

RM0440
28.6.25 TIMx timer encoder control register (TIMx_ECR)(x = 1, 8, 20)
Address offset: 0x058
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:27 Reserved, must be kept at reset value.
Bits 26:24 PWPRSC[2:0]: Pulse width prescaler
This bitfield sets the clock prescaler for the pulse generator, as following:
t
PWG
Bits 23:16 PW[7:0]: Pulse width
t
PW
Bits 15:8 Reserved, must be kept at reset value.
Bits 7:6 IPOS[1:0]: Index positioning
In quadrature encoder mode (SMS[3:0] = 0001, 0010, 0011, 1110, 1111), this bit indicates in
which AB input configuration the Index event resets the counter.
In directional clock mode or clock plus direction mode (SMS[3:0] = 1010, 1011, 1100, 1101),
these bits indicates on which level the Index event resets the counter. In bidirectional clock
mode, this applies for both clock inputs.
Note: IPOS[1] bit is not significant
Bit 5 FIDX: First index
This bit indicates if the first index only is taken into account
28 27 26 25
Res. PWPRSC[2:0]
rw rw
12 11 10 9
Res. Res. Res.
(PWPRSC[2:0])
= (2 ) x
This bitfield defines the pulse duration, as following:
= PW[7:0] x t
PWG
00: Index resets the counter when AB = 00
01: Index resets the counter when AB = 01
10: Index resets the counter when AB = 10
11: Index resets the counter when AB = 11
x0: Index resets the counter when clock is 0
x1: Index resets the counter when clock is 1
0: Index is always active
1: the first Index only resets the counter
Advanced-control timers (TIM1/TIM8/TIM20)
24 23 22
rw rw rw
8 7 6
Res. IPOS[1:0]
rw rw
t
tim_ker_ck
RM0440 Rev 4
21 20 19 18
PW[7:0]
rw rw rw rw
5 4 3 2
FIDX Res. Res.
rw rw
17 16
rw rw
1 0
IDIR[1:0] IE
rw rw
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