ST STM32G4 Series Reference Manual page 1427

RM0440
Bits 1:0 CC1S[1:0]: Capture/Compare 1 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC1 channel is configured as output
01: CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1
Others: Reserved
Note: CC1S bits are writable only when the channel is OFF (CC1E = '0' in TIMx_CCER).
30.8.7 TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 16 to 17)
Address offset: 0x18
Reset value: 0x0000 0000
The same register can be used for output compare mode (this section) or for input capture
mode (previous section). The direction of a channel is defined by configuring the
corresponding CCxS bits. All the other bits of this register have a different function for input
capture and for output compare modes. It is possible to combine both modes independently
(e.g. channel 1 in input capture mode and channel 2 in output compare mode).
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Output compare mode:
Bits 31:17 Reserved, must be kept at reset value.
Bits 15:8 Reserved, must be kept at reset value.
Bit 7 OC1CE: Output Compare 1 clear enable
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
0: tim_oc1ref is not affected by the tim_ocref_clr input.
1: tim_oc1ref is cleared as soon as a High level is detected on tim_ocref_clr input.
General-purpose timers (TIM15/TIM16/TIM17)
24 23 22
Res. Res. Res.
8 7 6
Res. OC1CE OC1M[2:0]
rw rw
RM0440 Rev 4
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
OC1PE OC1FE
rw rw rw rw
17 16
OC1M
Res.
[3]
rw
1 0
CC1S[1:0]
rw rw
1427/2126
1445