ST STM32G4 Series Reference Manual page 711

RM0440
21.6.17 ADC offset y register (ADC_OFRy)
Address offset: 0x60 + 0x04 * (y -1), (y= 1 to 4)
Reset value: 0x0000 0000
31 30 29 28
OFFSETy
OFFSETy_CH[4:0]
_EN
rw rw rw rw
15 14 13 12
Res. Res. Res. Res.
Bit 31 OFFSETy_EN: Offset y enable
Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0
Bits 30:26 OFFSETy_CH[4:0]: Channel selection for the data offset y
Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0
Bit 25 SATEN: Saturation enable
Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0
27 26 25
SATEN
rw rw rw
11 10 9
rw rw rw
This bit is written by software to enable or disable the offset programmed into bits
OFFSETy[11:0].
(which ensures that no conversion is ongoing).
These bits are written by software to define the channel to which the offset programmed into
bits OFFSETy[11:0] will apply.
(which ensures that no conversion is ongoing).
Some channels are not connected physically and must not be selected for the data
offset y.
This bit is set and cleared by software to enable the saturation at 0x000 and 0xFFF for the
offset function.
0: No saturation control, offset result can be signed
1: Saturation enabled, offset result unsigned and saturated at 0x000 and 0xFFF
(which ensures that no conversion is ongoing).
24 23 22
OFFSE
Res. Res. Res.
TPOS
rw
8 7 6
OFFSETy[11:0]
rw rw rw
RM0440 Rev 4
Analog-to-digital converters (ADC)
21 20 19 18
Res. Res. Res.
5 4 3 2
rw rw rw rw
17 16
Res. Res.
1 0
rw rw
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